pmpcfg14

PMP Configuration Register 14

PMP entry configuration

Attributes

CSR Address

0x3ae

Defining extension

  • Smpmp, version >= 0

Length

64-bit

Privilege Mode

M

Format

pmpcfg14 format
Figure 1. pmpcfg14 format

Field Summary

Name Location Type Reset Value

pmp56cfg

7:0

RO

0

pmp57cfg

15:8

RO

0

pmp58cfg

23:16

RO

0

pmp59cfg

31:24

RO

0

pmp60cfg

39:32

RO

0

pmp61cfg

47:40

RO

0

pmp62cfg

55:48

RO

0

pmp63cfg

63:56

RO

0

Fields

pmp56cfg

Location

pmpcfg14[7:0]

Description

PMP configuration for entry 56

The bits are as follows:

Name

Location

Description +

L

7

Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.

-

6:5

Reserved Writes shall be ignored.

A

4:3

Address matching mode. One of:

+ [when="PMP_GRANULARITY < 2"] * OFF (0) - Null region (disabled) * TOR (1) - Top of range * NA4 (2) - Naturally aligned four-byte region * NAPOT (3) - Natrually aligned power of two

+ [when="PMP_GRANULARITY >= 2"] * OFF (0) - Null region (disabled) * TOR (1) - Top of range * NAPOT (3) - Natrually aligned power of two

+

Naturally aligned four-byte region, NA4 (2), is not valid (not needed when the PMP granularity is larger than 4 bytes).

+

X

2

When clear, instruction fetchs cause an Access Fault for the matching region and privilege mode.

W

1

When clear, stores and AMOs cause an Access Fault for the matching region and privilege mode.

R

0

When clear, loads cause an Access Fault for the matching region and privilege mode.

The combination of R = 0, W = 1 is reserved.

Type

RO

Read-Only

Field has a hardwired value that does not change. Writes to an RO field are ignored.

Reset value

0

Software write

This field has special behavior when written by software (e.g., through csrrw).

When software tries to write csr_value, the field will be written with the return value of the function below.

if (! {
  if ((false) || csr_value.pmp56cfg & 0x18) != 0x10 {
    return csr_value.pmp56cfg;
  }
}
return CSR[pmpcfg14].pmp56cfg;

pmp57cfg

Location

pmpcfg14[15:8]

Description

PMP configuration for entry 57

The bits are as follows:

Name

Location

Description +

L

15

Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.

-

14:13

Reserved Writes shall be ignored.

A

12:11

Address matching mode. One of:

+ [when="PMP_GRANULARITY < 2"] * OFF (0) - Null region (disabled) * TOR (1) - Top of range * NA4 (2) - Naturally aligned four-byte region * NAPOT (3) - Natrually aligned power of two

+ [when="PMP_GRANULARITY >= 2"] * OFF (0) - Null region (disabled) * TOR (1) - Top of range * NAPOT (3) - Natrually aligned power of two

+

Naturally aligned four-byte region, NA4 (2), is not valid (not needed when the PMP granularity is larger than 4 bytes).

+

X

10

When clear, instruction fetchs cause an Access Fault for the matching region and privilege mode.

W

9

When clear, stores and AMOs cause an Access Fault for the matching region and privilege mode.

R

8

When clear, loads cause an Access Fault for the matching region and privilege mode.

The combination of R = 0, W = 1 is reserved.

Type

RO

Read-Only

Field has a hardwired value that does not change. Writes to an RO field are ignored.

Reset value

0

Software write

This field has special behavior when written by software (e.g., through csrrw).

When software tries to write csr_value, the field will be written with the return value of the function below.

if (! {
  if ((false) || csr_value.pmp57cfg & 0x18) != 0x10 {
    return csr_value.pmp57cfg;
  }
}
return CSR[pmpcfg14].pmp57cfg;

pmp58cfg

Location

pmpcfg14[23:16]

Description

PMP configuration for entry 58

The bits are as follows:

Name

Location

Description +

L

23

Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.

-

22:21

Reserved Writes shall be ignored.

A

20:19

Address matching mode. One of:

+ [when="PMP_GRANULARITY < 2"] * OFF (0) - Null region (disabled) * TOR (1) - Top of range * NA4 (2) - Naturally aligned four-byte region * NAPOT (3) - Natrually aligned power of two

+ [when="PMP_GRANULARITY >= 2"] * OFF (0) - Null region (disabled) * TOR (1) - Top of range * NAPOT (3) - Natrually aligned power of two

+

Naturally aligned four-byte region, NA4 (2), is not valid (not needed when the PMP granularity is larger than 4 bytes).

+

X

18

When clear, instruction fetchs cause an Access Fault for the matching region and privilege mode.

W

17

When clear, stores and AMOs cause an Access Fault for the matching region and privilege mode.

R

16

When clear, loads cause an Access Fault for the matching region and privilege mode.

The combination of R = 0, W = 1 is reserved.

Type

RO

Read-Only

Field has a hardwired value that does not change. Writes to an RO field are ignored.

Reset value

0

Software write

This field has special behavior when written by software (e.g., through csrrw).

When software tries to write csr_value, the field will be written with the return value of the function below.

if (! {
  if ((false) || csr_value.pmp58cfg & 0x18) != 0x10 {
    return csr_value.pmp58cfg;
  }
}
return CSR[pmpcfg14].pmp58cfg;

pmp59cfg

Location

pmpcfg14[31:24]

Description

PMP configuration for entry 59

The bits are as follows:

Name

Location

Description +

L

31

Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.

-

30:29

Reserved Writes shall be ignored.

A

28:27

Address matching mode. One of:

+ [when="PMP_GRANULARITY < 2"] * OFF (0) - Null region (disabled) * TOR (1) - Top of range * NA4 (2) - Naturally aligned four-byte region * NAPOT (3) - Natrually aligned power of two

+ [when="PMP_GRANULARITY >= 2"] * OFF (0) - Null region (disabled) * TOR (1) - Top of range * NAPOT (3) - Natrually aligned power of two

+

Naturally aligned four-byte region, NA4 (2), is not valid (not needed when the PMP granularity is larger than 4 bytes).

+

X

26

When clear, instruction fetchs cause an Access Fault for the matching region and privilege mode.

W

25

When clear, stores and AMOs cause an Access Fault for the matching region and privilege mode.

R

24

When clear, loads cause an Access Fault for the matching region and privilege mode.

The combination of R = 0, W = 1 is reserved.

Type

RO

Read-Only

Field has a hardwired value that does not change. Writes to an RO field are ignored.

Reset value

0

Software write

This field has special behavior when written by software (e.g., through csrrw).

When software tries to write csr_value, the field will be written with the return value of the function below.

if (! {
  if ((false) || csr_value.pmp59cfg & 0x18) != 0x10 {
    return csr_value.pmp59cfg;
  }
}
return CSR[pmpcfg14].pmp59cfg;

pmp60cfg

Location

pmpcfg14[39:32]

Description

PMP configuration for entry 60

The bits are as follows:

Name

Location

Description +

L

39

Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.

-

38:37

Reserved Writes shall be ignored.

A

36:35

Address matching mode. One of:

+ [when="PMP_GRANULARITY < 2"] * OFF (0) - Null region (disabled) * TOR (1) - Top of range * NA4 (2) - Naturally aligned four-byte region * NAPOT (3) - Natrually aligned power of two

+ [when="PMP_GRANULARITY >= 2"] * OFF (0) - Null region (disabled) * TOR (1) - Top of range * NAPOT (3) - Natrually aligned power of two

+

Naturally aligned four-byte region, NA4 (2), is not valid (not needed when the PMP granularity is larger than 4 bytes).

+

X

34

When clear, instruction fetchs cause an Access Fault for the matching region and privilege mode.

W

33

When clear, stores and AMOs cause an Access Fault for the matching region and privilege mode.

R

32

When clear, loads cause an Access Fault for the matching region and privilege mode.

The combination of R = 0, W = 1 is reserved.

Type

RO

Read-Only

Field has a hardwired value that does not change. Writes to an RO field are ignored.

Reset value

0

Software write

This field has special behavior when written by software (e.g., through csrrw).

When software tries to write csr_value, the field will be written with the return value of the function below.

if (! {
  if ((false) || csr_value.pmp60cfg & 0x18) != 0x10 {
    return csr_value.pmp60cfg;
  }
}
return CSR[pmpcfg14].pmp60cfg;

pmp61cfg

Location

pmpcfg14[47:40]

Description

PMP configuration for entry 61

The bits are as follows:

Name

Location

Description +

L

47

Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.

-

46:45

Reserved Writes shall be ignored.

A

44:43

Address matching mode. One of:

+ [when="PMP_GRANULARITY < 2"] * OFF (0) - Null region (disabled) * TOR (1) - Top of range * NA4 (2) - Naturally aligned four-byte region * NAPOT (3) - Natrually aligned power of two

+ [when="PMP_GRANULARITY >= 2"] * OFF (0) - Null region (disabled) * TOR (1) - Top of range * NAPOT (3) - Natrually aligned power of two

+

Naturally aligned four-byte region, NA4 (2), is not valid (not needed when the PMP granularity is larger than 4 bytes).

+

X

42

When clear, instruction fetchs cause an Access Fault for the matching region and privilege mode.

W

41

When clear, stores and AMOs cause an Access Fault for the matching region and privilege mode.

R

40

When clear, loads cause an Access Fault for the matching region and privilege mode.

The combination of R = 0, W = 1 is reserved.

Type

RO

Read-Only

Field has a hardwired value that does not change. Writes to an RO field are ignored.

Reset value

0

Software write

This field has special behavior when written by software (e.g., through csrrw).

When software tries to write csr_value, the field will be written with the return value of the function below.

if (! {
  if ((false) || csr_value.pmp61cfg & 0x18) != 0x10 {
    return csr_value.pmp61cfg;
  }
}
return CSR[pmpcfg14].pmp61cfg;

pmp62cfg

Location

pmpcfg14[55:48]

Description

PMP configuration for entry 62

The bits are as follows:

Name

Location

Description +

L

55

Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.

-

54:53

Reserved Writes shall be ignored.

A

52:51

Address matching mode. One of:

+ [when="PMP_GRANULARITY < 2"] * OFF (0) - Null region (disabled) * TOR (1) - Top of range * NA4 (2) - Naturally aligned four-byte region * NAPOT (3) - Natrually aligned power of two

+ [when="PMP_GRANULARITY >= 2"] * OFF (0) - Null region (disabled) * TOR (1) - Top of range * NAPOT (3) - Natrually aligned power of two

+

Naturally aligned four-byte region, NA4 (2), is not valid (not needed when the PMP granularity is larger than 4 bytes).

+

X

50

When clear, instruction fetchs cause an Access Fault for the matching region and privilege mode.

W

49

When clear, stores and AMOs cause an Access Fault for the matching region and privilege mode.

R

48

When clear, loads cause an Access Fault for the matching region and privilege mode.

The combination of R = 0, W = 1 is reserved.

Type

RO

Read-Only

Field has a hardwired value that does not change. Writes to an RO field are ignored.

Reset value

0

Software write

This field has special behavior when written by software (e.g., through csrrw).

When software tries to write csr_value, the field will be written with the return value of the function below.

if (! {
  if ((false) || csr_value.pmp62cfg & 0x18) != 0x10 {
    return csr_value.pmp62cfg;
  }
}
return CSR[pmpcfg14].pmp62cfg;

pmp63cfg

Location

pmpcfg14[63:56]

Description

PMP configuration for entry 63

The bits are as follows:

Name

Location

Description +

L

63

Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.

-

62:61

Reserved Writes shall be ignored.

A

60:59

Address matching mode. One of:

+ [when="PMP_GRANULARITY < 2"] * OFF (0) - Null region (disabled) * TOR (1) - Top of range * NA4 (2) - Naturally aligned four-byte region * NAPOT (3) - Natrually aligned power of two

+ [when="PMP_GRANULARITY >= 2"] * OFF (0) - Null region (disabled) * TOR (1) - Top of range * NAPOT (3) - Natrually aligned power of two

+

Naturally aligned four-byte region, NA4 (2), is not valid (not needed when the PMP granularity is larger than 4 bytes).

+

X

58

When clear, instruction fetchs cause an Access Fault for the matching region and privilege mode.

W

57

When clear, stores and AMOs cause an Access Fault for the matching region and privilege mode.

R

56

When clear, loads cause an Access Fault for the matching region and privilege mode.

The combination of R = 0, W = 1 is reserved.

Type

RO

Read-Only

Field has a hardwired value that does not change. Writes to an RO field are ignored.

Reset value

0

Software write

This field has special behavior when written by software (e.g., through csrrw).

When software tries to write csr_value, the field will be written with the return value of the function below.

if (! {
  if ((false) || csr_value.pmp63cfg & 0x18) != 0x10 {
    return csr_value.pmp63cfg;
  }
}
return CSR[pmpcfg14].pmp63cfg;