pmpcfg12

PMP Configuration Register 12

PMP entry configuration

Attributes

CSR Address

0x3ac

Defining extension

  • Smpmp, version >= 0

Length

64-bit

Privilege Mode

M

Format

pmpcfg12 format
Figure 1. pmpcfg12 format

Field Summary

Name Location Type Reset Value

pmp48cfg

7:0

RO

0

pmp49cfg

15:8

RO

0

pmp50cfg

23:16

RO

0

pmp51cfg

31:24

RO

0

pmp52cfg

39:32

RO

0

pmp53cfg

47:40

RO

0

pmp54cfg

55:48

RO

0

pmp55cfg

63:56

RO

0

Fields

pmp48cfg

Location

pmpcfg12[7:0]

Description

PMP configuration for entry 48

The bits are as follows:

Name

Location

Description +

L

7

Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.

-

6:5

Reserved Writes shall be ignored.

A

4:3

Address matching mode. One of:

+ [when="PMP_GRANULARITY < 2"] * OFF (0) - Null region (disabled) * TOR (1) - Top of range * NA4 (2) - Naturally aligned four-byte region * NAPOT (3) - Natrually aligned power of two

+ [when="PMP_GRANULARITY >= 2"] * OFF (0) - Null region (disabled) * TOR (1) - Top of range * NAPOT (3) - Natrually aligned power of two

+

Naturally aligned four-byte region, NA4 (2), is not valid (not needed when the PMP granularity is larger than 4 bytes).

+

X

2

When clear, instruction fetchs cause an Access Fault for the matching region and privilege mode.

W

1

When clear, stores and AMOs cause an Access Fault for the matching region and privilege mode.

R

0

When clear, loads cause an Access Fault for the matching region and privilege mode.

The combination of R = 0, W = 1 is reserved.

Type

RO

Read-Only

Field has a hardwired value that does not change. Writes to an RO field are ignored.

Reset value

0

Software write

This field has special behavior when written by software (e.g., through csrrw).

When software tries to write csr_value, the field will be written with the return value of the function below.

if (! {
  if ((false) || csr_value.pmp48cfg & 0x18) != 0x10 {
    return csr_value.pmp48cfg;
  }
}
return CSR[pmpcfg12].pmp48cfg;

pmp49cfg

Location

pmpcfg12[15:8]

Description

PMP configuration for entry 49

The bits are as follows:

Name

Location

Description +

L

15

Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.

-

14:13

Reserved Writes shall be ignored.

A

12:11

Address matching mode. One of:

+ [when="PMP_GRANULARITY < 2"] * OFF (0) - Null region (disabled) * TOR (1) - Top of range * NA4 (2) - Naturally aligned four-byte region * NAPOT (3) - Natrually aligned power of two

+ [when="PMP_GRANULARITY >= 2"] * OFF (0) - Null region (disabled) * TOR (1) - Top of range * NAPOT (3) - Natrually aligned power of two

+

Naturally aligned four-byte region, NA4 (2), is not valid (not needed when the PMP granularity is larger than 4 bytes).

+

X

10

When clear, instruction fetchs cause an Access Fault for the matching region and privilege mode.

W

9

When clear, stores and AMOs cause an Access Fault for the matching region and privilege mode.

R

8

When clear, loads cause an Access Fault for the matching region and privilege mode.

The combination of R = 0, W = 1 is reserved.

Type

RO

Read-Only

Field has a hardwired value that does not change. Writes to an RO field are ignored.

Reset value

0

Software write

This field has special behavior when written by software (e.g., through csrrw).

When software tries to write csr_value, the field will be written with the return value of the function below.

if (! {
  if ((false) || csr_value.pmp49cfg & 0x18) != 0x10 {
    return csr_value.pmp49cfg;
  }
}
return CSR[pmpcfg12].pmp49cfg;

pmp50cfg

Location

pmpcfg12[23:16]

Description

PMP configuration for entry 50

The bits are as follows:

Name

Location

Description +

L

23

Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.

-

22:21

Reserved Writes shall be ignored.

A

20:19

Address matching mode. One of:

+ [when="PMP_GRANULARITY < 2"] * OFF (0) - Null region (disabled) * TOR (1) - Top of range * NA4 (2) - Naturally aligned four-byte region * NAPOT (3) - Natrually aligned power of two

+ [when="PMP_GRANULARITY >= 2"] * OFF (0) - Null region (disabled) * TOR (1) - Top of range * NAPOT (3) - Natrually aligned power of two

+

Naturally aligned four-byte region, NA4 (2), is not valid (not needed when the PMP granularity is larger than 4 bytes).

+

X

18

When clear, instruction fetchs cause an Access Fault for the matching region and privilege mode.

W

17

When clear, stores and AMOs cause an Access Fault for the matching region and privilege mode.

R

16

When clear, loads cause an Access Fault for the matching region and privilege mode.

The combination of R = 0, W = 1 is reserved.

Type

RO

Read-Only

Field has a hardwired value that does not change. Writes to an RO field are ignored.

Reset value

0

Software write

This field has special behavior when written by software (e.g., through csrrw).

When software tries to write csr_value, the field will be written with the return value of the function below.

if (! {
  if ((false) || csr_value.pmp50cfg & 0x18) != 0x10 {
    return csr_value.pmp50cfg;
  }
}
return CSR[pmpcfg12].pmp50cfg;

pmp51cfg

Location

pmpcfg12[31:24]

Description

PMP configuration for entry 51

The bits are as follows:

Name

Location

Description +

L

31

Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.

-

30:29

Reserved Writes shall be ignored.

A

28:27

Address matching mode. One of:

+ [when="PMP_GRANULARITY < 2"] * OFF (0) - Null region (disabled) * TOR (1) - Top of range * NA4 (2) - Naturally aligned four-byte region * NAPOT (3) - Natrually aligned power of two

+ [when="PMP_GRANULARITY >= 2"] * OFF (0) - Null region (disabled) * TOR (1) - Top of range * NAPOT (3) - Natrually aligned power of two

+

Naturally aligned four-byte region, NA4 (2), is not valid (not needed when the PMP granularity is larger than 4 bytes).

+

X

26

When clear, instruction fetchs cause an Access Fault for the matching region and privilege mode.

W

25

When clear, stores and AMOs cause an Access Fault for the matching region and privilege mode.

R

24

When clear, loads cause an Access Fault for the matching region and privilege mode.

The combination of R = 0, W = 1 is reserved.

Type

RO

Read-Only

Field has a hardwired value that does not change. Writes to an RO field are ignored.

Reset value

0

Software write

This field has special behavior when written by software (e.g., through csrrw).

When software tries to write csr_value, the field will be written with the return value of the function below.

if (! {
  if ((false) || csr_value.pmp51cfg & 0x18) != 0x10 {
    return csr_value.pmp51cfg;
  }
}
return CSR[pmpcfg12].pmp51cfg;

pmp52cfg

Location

pmpcfg12[39:32]

Description

PMP configuration for entry 52

The bits are as follows:

Name

Location

Description +

L

39

Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.

-

38:37

Reserved Writes shall be ignored.

A

36:35

Address matching mode. One of:

+ [when="PMP_GRANULARITY < 2"] * OFF (0) - Null region (disabled) * TOR (1) - Top of range * NA4 (2) - Naturally aligned four-byte region * NAPOT (3) - Natrually aligned power of two

+ [when="PMP_GRANULARITY >= 2"] * OFF (0) - Null region (disabled) * TOR (1) - Top of range * NAPOT (3) - Natrually aligned power of two

+

Naturally aligned four-byte region, NA4 (2), is not valid (not needed when the PMP granularity is larger than 4 bytes).

+

X

34

When clear, instruction fetchs cause an Access Fault for the matching region and privilege mode.

W

33

When clear, stores and AMOs cause an Access Fault for the matching region and privilege mode.

R

32

When clear, loads cause an Access Fault for the matching region and privilege mode.

The combination of R = 0, W = 1 is reserved.

Type

RO

Read-Only

Field has a hardwired value that does not change. Writes to an RO field are ignored.

Reset value

0

Software write

This field has special behavior when written by software (e.g., through csrrw).

When software tries to write csr_value, the field will be written with the return value of the function below.

if (! {
  if ((false) || csr_value.pmp52cfg & 0x18) != 0x10 {
    return csr_value.pmp52cfg;
  }
}
return CSR[pmpcfg12].pmp52cfg;

pmp53cfg

Location

pmpcfg12[47:40]

Description

PMP configuration for entry 53

The bits are as follows:

Name

Location

Description +

L

47

Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.

-

46:45

Reserved Writes shall be ignored.

A

44:43

Address matching mode. One of:

+ [when="PMP_GRANULARITY < 2"] * OFF (0) - Null region (disabled) * TOR (1) - Top of range * NA4 (2) - Naturally aligned four-byte region * NAPOT (3) - Natrually aligned power of two

+ [when="PMP_GRANULARITY >= 2"] * OFF (0) - Null region (disabled) * TOR (1) - Top of range * NAPOT (3) - Natrually aligned power of two

+

Naturally aligned four-byte region, NA4 (2), is not valid (not needed when the PMP granularity is larger than 4 bytes).

+

X

42

When clear, instruction fetchs cause an Access Fault for the matching region and privilege mode.

W

41

When clear, stores and AMOs cause an Access Fault for the matching region and privilege mode.

R

40

When clear, loads cause an Access Fault for the matching region and privilege mode.

The combination of R = 0, W = 1 is reserved.

Type

RO

Read-Only

Field has a hardwired value that does not change. Writes to an RO field are ignored.

Reset value

0

Software write

This field has special behavior when written by software (e.g., through csrrw).

When software tries to write csr_value, the field will be written with the return value of the function below.

if (! {
  if ((false) || csr_value.pmp53cfg & 0x18) != 0x10 {
    return csr_value.pmp53cfg;
  }
}
return CSR[pmpcfg12].pmp53cfg;

pmp54cfg

Location

pmpcfg12[55:48]

Description

PMP configuration for entry 54

The bits are as follows:

Name

Location

Description +

L

55

Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.

-

54:53

Reserved Writes shall be ignored.

A

52:51

Address matching mode. One of:

+ [when="PMP_GRANULARITY < 2"] * OFF (0) - Null region (disabled) * TOR (1) - Top of range * NA4 (2) - Naturally aligned four-byte region * NAPOT (3) - Natrually aligned power of two

+ [when="PMP_GRANULARITY >= 2"] * OFF (0) - Null region (disabled) * TOR (1) - Top of range * NAPOT (3) - Natrually aligned power of two

+

Naturally aligned four-byte region, NA4 (2), is not valid (not needed when the PMP granularity is larger than 4 bytes).

+

X

50

When clear, instruction fetchs cause an Access Fault for the matching region and privilege mode.

W

49

When clear, stores and AMOs cause an Access Fault for the matching region and privilege mode.

R

48

When clear, loads cause an Access Fault for the matching region and privilege mode.

The combination of R = 0, W = 1 is reserved.

Type

RO

Read-Only

Field has a hardwired value that does not change. Writes to an RO field are ignored.

Reset value

0

Software write

This field has special behavior when written by software (e.g., through csrrw).

When software tries to write csr_value, the field will be written with the return value of the function below.

if (! {
  if ((false) || csr_value.pmp54cfg & 0x18) != 0x10 {
    return csr_value.pmp54cfg;
  }
}
return CSR[pmpcfg12].pmp54cfg;

pmp55cfg

Location

pmpcfg12[63:56]

Description

PMP configuration for entry 55

The bits are as follows:

Name

Location

Description +

L

63

Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.

-

62:61

Reserved Writes shall be ignored.

A

60:59

Address matching mode. One of:

+ [when="PMP_GRANULARITY < 2"] * OFF (0) - Null region (disabled) * TOR (1) - Top of range * NA4 (2) - Naturally aligned four-byte region * NAPOT (3) - Natrually aligned power of two

+ [when="PMP_GRANULARITY >= 2"] * OFF (0) - Null region (disabled) * TOR (1) - Top of range * NAPOT (3) - Natrually aligned power of two

+

Naturally aligned four-byte region, NA4 (2), is not valid (not needed when the PMP granularity is larger than 4 bytes).

+

X

58

When clear, instruction fetchs cause an Access Fault for the matching region and privilege mode.

W

57

When clear, stores and AMOs cause an Access Fault for the matching region and privilege mode.

R

56

When clear, loads cause an Access Fault for the matching region and privilege mode.

The combination of R = 0, W = 1 is reserved.

Type

RO

Read-Only

Field has a hardwired value that does not change. Writes to an RO field are ignored.

Reset value

0

Software write

This field has special behavior when written by software (e.g., through csrrw).

When software tries to write csr_value, the field will be written with the return value of the function below.

if (! {
  if ((false) || csr_value.pmp55cfg & 0x18) != 0x10 {
    return csr_value.pmp55cfg;
  }
}
return CSR[pmpcfg12].pmp55cfg;