fclass.s

Floating-Point Classify Single-Precision

This instruction is defined by:

Encoding

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Synopsis

The fclass.s instruction examines the value in floating-point register fs1 and writes to integer register xd a 10-bit mask that indicates the class of the floating-point number.

The format of the mask is described in the table below. The corresponding bit in xd will be set if the property is true and clear otherwise. All other bits in xd are cleared. Note that exactly one bit in xd will be set. fclass.s does not set the floating-point exception flags.

Table 1. Format of result of fclass instruction.
xd bit Meaning

0

fs1 is .

1

fs1 is a negative normal number.

2

fs1 is a negative subnormal number.

3

fs1 is .

4

fs1 is .

5

fs1 is a positive subnormal number.

6

fs1 is a positive normal number.

7

fs1 is .

8

fs1 is a signaling NaN.

9

fs1 is a quiet NaN.

Access

M HS U VS VU

Always

Always

Always

Always

Always

Decode Variables

Bits<5> fs1 = $encoding[19:15];
Bits<5> xd = $encoding[11:7];

Execution

  • Pruned, XLEN == 64

  • Original

check_f_ok($encoding);
Bits<32> sp_value = f[fs1][31:0];
if (is_sp_neg_inf?(sp_value)) {
  X[xd] = 1;
} else if (is_sp_neg_norm?(sp_value)) {
  X[xd] = 2;
} else if (is_sp_neg_subnorm?(sp_value)) {
  X[xd] = 4;
} else if (is_sp_neg_zero?(sp_value)) {
  X[xd] = 8;
} else if (is_sp_pos_zero?(sp_value)) {
  X[xd] = 16;
} else if (is_sp_pos_subnorm?(sp_value)) {
  X[xd] = 32;
} else if (is_sp_pos_norm?(sp_value)) {
  X[xd] = 64;
} else if (is_sp_pos_inf?(sp_value)) {
  X[xd] = 128;
} else if (is_sp_signaling_nan?(sp_value)) {
  X[xd] = 256;
} else {
  assert(is_sp_quiet_nan?(sp_value), "Unexpected SP value");
  X[xd] = 512;
}
check_f_ok($encoding);
Bits<32> sp_value = f[fs1][31:0];
if (is_sp_neg_inf?(sp_value)) {
  X[xd] = 1 << 0;
} else if (is_sp_neg_norm?(sp_value)) {
  X[xd] = 1 `<< 1;
} else if (is_sp_neg_subnorm?(sp_value)) {
  X[xd] = 1 `<< 2;
} else if (is_sp_neg_zero?(sp_value)) {
  X[xd] = 1 `<< 3;
} else if (is_sp_pos_zero?(sp_value)) {
  X[xd] = 1 `<< 4;
} else if (is_sp_pos_subnorm?(sp_value)) {
  X[xd] = 1 `<< 5;
} else if (is_sp_pos_norm?(sp_value)) {
  X[xd] = 1 `<< 6;
} else if (is_sp_pos_inf?(sp_value)) {
  X[xd] = 1 `<< 7;
} else if (is_sp_signaling_nan?(sp_value)) {
  X[xd] = 1 `<< 8;
} else {
  assert(is_sp_quiet_nan?(sp_value), "Unexpected SP value");
  X[xd] = 1 `<< 9;
}

Exceptions

This instruction may result in the following synchronous exceptions:

  • IllegalInstruction