scountovf

Supervisor Count Overflow

A 32-bit read-only register that contains shadow copies of the OF bits in the 29 mhpmevent CSRs (mhpmevent3 - mhpmevent31) — where scountovf bit X corresponds to mhpmeventX.

This register enables supervisor-level overflow interrupt handler software to quickly and easily determine which counter(s) have overflowed without needing to make an execution environment call up to M-mode.

Read access to bit X is subject to the same mcounteren (or mcounteren and hcounteren) CSRs that mediate access to the hpmcounter CSRs by S-mode (or VS-mode).

In M-mode, scountovf bit X is always readable. In S/HS-mode, scountovf bit X is readable when mcounteren bit X is set, and otherwise reads as zero. Similarly, in VS-mode, it is readable when both mcounteren and hcounteren bit X are set.

Attributes

CSR Address	0xda0
Defining extension	Sscofpmf
Length	32-bit
Privilege Mode	S

CSR Address

0xda0

Defining extension

Sscofpmf

Length

32-bit

Privilege Mode

Format

Figure 1. scountovf format

Field Summary

Name	Location	Type	Reset Value
`OF3`	3	RO	UNDEFINED_LEGAL
`OF4`	4	RO	UNDEFINED_LEGAL
`OF5`	5	RO	UNDEFINED_LEGAL
`OF6`	6	RO	UNDEFINED_LEGAL
`OF7`	7	RO	UNDEFINED_LEGAL
`OF8`	8	RO	UNDEFINED_LEGAL
`OF9`	9	RO	UNDEFINED_LEGAL
`OF10`	10	RO	UNDEFINED_LEGAL
`OF11`	11	RO-H	0
`OF12`	12	RO-H	0
`OF13`	13	RO-H	0
`OF14`	14	RO-H	0
`OF15`	15	RO-H	0
`OF16`	16	RO-H	0
`OF17`	17	RO-H	0
`OF18`	18	RO-H	0
`OF19`	19	RO-H	0
`OF20`	20	RO-H	0
`OF21`	21	RO-H	0
`OF22`	22	RO-H	0
`OF23`	23	RO-H	0
`OF24`	24	RO-H	0
`OF25`	25	RO-H	0
`OF26`	26	RO-H	0
`OF27`	27	RO-H	0
`OF28`	28	RO-H	0
`OF29`	29	RO-H	0
`OF30`	30	RO-H	0
`OF31`	31	RO-H	0

Fields

`OF3`

Location: scountovf[3]
Description

Shadow copy of mhpmevent3 overflow (OF) bit.

This field is read-only zero because the counter is not enabled.

Type

RO	Read-Only Field has a hardwired value that does not change. Writes to an RO field are ignored.

Reset value: UNDEFINED_LEGAL

`OF4`

Location: scountovf[4]
Description

Shadow copy of mhpmevent4 overflow (OF) bit.

This field is read-only zero because the counter is not enabled.

Type

RO	Read-Only Field has a hardwired value that does not change. Writes to an RO field are ignored.

Reset value: UNDEFINED_LEGAL

`OF5`

Location: scountovf[5]
Description

Shadow copy of mhpmevent5 overflow (OF) bit.

This field is read-only zero because the counter is not enabled.

Type

RO	Read-Only Field has a hardwired value that does not change. Writes to an RO field are ignored.

Reset value: UNDEFINED_LEGAL

`OF6`

Location: scountovf[6]
Description

Shadow copy of mhpmevent6 overflow (OF) bit.

This field is read-only zero because the counter is not enabled.

Type

RO	Read-Only Field has a hardwired value that does not change. Writes to an RO field are ignored.

Reset value: UNDEFINED_LEGAL

`OF7`

Location: scountovf[7]
Description

Shadow copy of mhpmevent7 overflow (OF) bit.

This field is read-only zero because the counter is not enabled.

Type

RO	Read-Only Field has a hardwired value that does not change. Writes to an RO field are ignored.

Reset value: UNDEFINED_LEGAL

`OF8`

Location: scountovf[8]
Description

Shadow copy of mhpmevent8 overflow (OF) bit.

This field is read-only zero because the counter is not enabled.

Type

RO	Read-Only Field has a hardwired value that does not change. Writes to an RO field are ignored.

Reset value: UNDEFINED_LEGAL

`OF9`

Location: scountovf[9]
Description

Shadow copy of mhpmevent9 overflow (OF) bit.

This field is read-only zero because the counter is not enabled.

Type

RO	Read-Only Field has a hardwired value that does not change. Writes to an RO field are ignored.

Reset value: UNDEFINED_LEGAL

`OF10`

Location: scountovf[10]
Description

Shadow copy of mhpmevent10 overflow (OF) bit.

This field is read-only zero because the counter is not enabled.

Type

RO	Read-Only Field has a hardwired value that does not change. Writes to an RO field are ignored.

Reset value: UNDEFINED_LEGAL

`OF11`

Location: scountovf[11]
Description

Shadow copy of mhpmevent11 overflow (OF) bit.

This field is read-only zero because the counter is not enabled.

Type

RO-H	Read-Only with Hardware update Writes are ignored. Reads reflect a value dynamically generated by hardware.

Reset value: 0

`OF12`

Location: scountovf[12]
Description

Shadow copy of mhpmevent12 overflow (OF) bit.

This field is read-only zero because the counter is not enabled.

Type

RO-H	Read-Only with Hardware update Writes are ignored. Reads reflect a value dynamically generated by hardware.

Reset value: 0

`OF13`

Location: scountovf[13]
Description

Shadow copy of mhpmevent13 overflow (OF) bit.

This field is read-only zero because the counter is not enabled.

Type

RO-H	Read-Only with Hardware update Writes are ignored. Reads reflect a value dynamically generated by hardware.

Reset value: 0

`OF14`

Location: scountovf[14]
Description

Shadow copy of mhpmevent14 overflow (OF) bit.

This field is read-only zero because the counter is not enabled.

Type

RO-H	Read-Only with Hardware update Writes are ignored. Reads reflect a value dynamically generated by hardware.

Reset value: 0

`OF15`

Location: scountovf[15]
Description

Shadow copy of mhpmevent15 overflow (OF) bit.

This field is read-only zero because the counter is not enabled.

Type

RO-H	Read-Only with Hardware update Writes are ignored. Reads reflect a value dynamically generated by hardware.

Reset value: 0

`OF16`

Location: scountovf[16]
Description

Shadow copy of mhpmevent16 overflow (OF) bit.

This field is read-only zero because the counter is not enabled.

Type

RO-H	Read-Only with Hardware update Writes are ignored. Reads reflect a value dynamically generated by hardware.

Reset value: 0

`OF17`

Location: scountovf[17]
Description

Shadow copy of mhpmevent17 overflow (OF) bit.

This field is read-only zero because the counter is not enabled.

Type

RO-H	Read-Only with Hardware update Writes are ignored. Reads reflect a value dynamically generated by hardware.

Reset value: 0

`OF18`

Location: scountovf[18]
Description

Shadow copy of mhpmevent18 overflow (OF) bit.

This field is read-only zero because the counter is not enabled.

Type

RO-H	Read-Only with Hardware update Writes are ignored. Reads reflect a value dynamically generated by hardware.

Reset value: 0

`OF19`

Location: scountovf[19]
Description

Shadow copy of mhpmevent19 overflow (OF) bit.

This field is read-only zero because the counter is not enabled.

Type

RO-H	Read-Only with Hardware update Writes are ignored. Reads reflect a value dynamically generated by hardware.

Reset value: 0

`OF20`

Location: scountovf[20]
Description

Shadow copy of mhpmevent20 overflow (OF) bit.

This field is read-only zero because the counter is not enabled.

Type

RO-H	Read-Only with Hardware update Writes are ignored. Reads reflect a value dynamically generated by hardware.

Reset value: 0

`OF21`

Location: scountovf[21]
Description

Shadow copy of mhpmevent21 overflow (OF) bit.

This field is read-only zero because the counter is not enabled.

Type

RO-H	Read-Only with Hardware update Writes are ignored. Reads reflect a value dynamically generated by hardware.

Reset value: 0

`OF22`

Location: scountovf[22]
Description

Shadow copy of mhpmevent22 overflow (OF) bit.

This field is read-only zero because the counter is not enabled.

Type

RO-H	Read-Only with Hardware update Writes are ignored. Reads reflect a value dynamically generated by hardware.

Reset value: 0

`OF23`

Location: scountovf[23]
Description

Shadow copy of mhpmevent23 overflow (OF) bit.

This field is read-only zero because the counter is not enabled.

Type

RO-H	Read-Only with Hardware update Writes are ignored. Reads reflect a value dynamically generated by hardware.

Reset value: 0

`OF24`

Location: scountovf[24]
Description

Shadow copy of mhpmevent24 overflow (OF) bit.

This field is read-only zero because the counter is not enabled.

Type

RO-H	Read-Only with Hardware update Writes are ignored. Reads reflect a value dynamically generated by hardware.

Reset value: 0

`OF25`

Location: scountovf[25]
Description

Shadow copy of mhpmevent25 overflow (OF) bit.

This field is read-only zero because the counter is not enabled.

Type

RO-H	Read-Only with Hardware update Writes are ignored. Reads reflect a value dynamically generated by hardware.

Reset value: 0

`OF26`

Location: scountovf[26]
Description

Shadow copy of mhpmevent26 overflow (OF) bit.

This field is read-only zero because the counter is not enabled.

Type

RO-H	Read-Only with Hardware update Writes are ignored. Reads reflect a value dynamically generated by hardware.

Reset value: 0

`OF27`

Location: scountovf[27]
Description

Shadow copy of mhpmevent27 overflow (OF) bit.

This field is read-only zero because the counter is not enabled.

Type

RO-H	Read-Only with Hardware update Writes are ignored. Reads reflect a value dynamically generated by hardware.

Reset value: 0

`OF28`

Location: scountovf[28]
Description

Shadow copy of mhpmevent28 overflow (OF) bit.

This field is read-only zero because the counter is not enabled.

Type

RO-H	Read-Only with Hardware update Writes are ignored. Reads reflect a value dynamically generated by hardware.

Reset value: 0

`OF29`

Location: scountovf[29]
Description

Shadow copy of mhpmevent29 overflow (OF) bit.

This field is read-only zero because the counter is not enabled.

Type

RO-H	Read-Only with Hardware update Writes are ignored. Reads reflect a value dynamically generated by hardware.

Reset value: 0

`OF30`

Location: scountovf[30]
Description

Shadow copy of mhpmevent30 overflow (OF) bit.

This field is read-only zero because the counter is not enabled.

Type

RO-H	Read-Only with Hardware update Writes are ignored. Reads reflect a value dynamically generated by hardware.

Reset value: 0

`OF31`

Location: scountovf[31]
Description

Shadow copy of mhpmevent31 overflow (OF) bit.

This field is read-only zero because the counter is not enabled.

Type

RO-H	Read-Only with Hardware update Writes are ignored. Reads reflect a value dynamically generated by hardware.

Reset value: 0

Software read

This CSR may return a value that is different from what is stored in hardware.

Pruned
Original

Bits<32> mask;
if (mode() == PrivilegeMode::VS) {
  mask = $bits(CSR[CSR[mcounteren]]) & $bits(CSR[CSR[hcounteren]]);
} else {
  mask = $bits(CSR[CSR[mcounteren]]) & $bits(CSR[CSR[scounteren]]);
}
Bits<32> value = 0;
value = (CSR[mhpmevent3].OF << 3);
value = value | (CSR[mhpmevent4].OF << 4);
value = value | (CSR[mhpmevent5].OF << 5);
value = value | (CSR[mhpmevent6].OF << 6);
value = value | (CSR[mhpmevent7].OF << 7);
value = value | (CSR[mhpmevent8].OF << 8);
value = value | (CSR[mhpmevent9].OF << 9);
value = value | (CSR[mhpmevent10].OF << 10);
value = value | (CSR[mhpmevent11].OF << 11);
value = value | (CSR[mhpmevent12].OF << 12);
value = value | (CSR[mhpmevent13].OF << 13);
value = value | (CSR[mhpmevent14].OF << 14);
value = value | (CSR[mhpmevent15].OF << 15);
value = value | (CSR[mhpmevent16].OF << 16);
value = value | (CSR[mhpmevent17].OF << 17);
value = value | (CSR[mhpmevent18].OF << 18);
value = value | (CSR[mhpmevent19].OF << 19);
value = value | (CSR[mhpmevent20].OF << 20);
value = value | (CSR[mhpmevent21].OF << 21);
value = value | (CSR[mhpmevent22].OF << 22);
value = value | (CSR[mhpmevent23].OF << 23);
value = value | (CSR[mhpmevent24].OF << 24);
value = value | (CSR[mhpmevent25].OF << 25);
value = value | (CSR[mhpmevent26].OF << 26);
value = value | (CSR[mhpmevent27].OF << 27);
value = value | (CSR[mhpmevent28].OF << 28);
value = value | (CSR[mhpmevent29].OF << 29);
value = value | (CSR[mhpmevent30].OF << 30);
value = value | (CSR[mhpmevent31].OF << 31);
return value & mask;

Bits<32> mask;
if (mode() == PrivilegeMode::VS) {
  mask = $bits(CSR[CSR[mcounteren]]) & $bits(CSR[CSR[hcounteren]]);
} else {
  mask = $bits(CSR[CSR[mcounteren]]) & $bits(CSR[CSR[scounteren]]);
}
Bits<32> value = 0;
value = value | (CSR[mhpmevent3].OF << 3);
value = value | (CSR[mhpmevent4].OF << 4);
value = value | (CSR[mhpmevent5].OF << 5);
value = value | (CSR[mhpmevent6].OF << 6);
value = value | (CSR[mhpmevent7].OF << 7);
value = value | (CSR[mhpmevent8].OF << 8);
value = value | (CSR[mhpmevent9].OF << 9);
value = value | (CSR[mhpmevent10].OF << 10);
value = value | (CSR[mhpmevent11].OF << 11);
value = value | (CSR[mhpmevent12].OF << 12);
value = value | (CSR[mhpmevent13].OF << 13);
value = value | (CSR[mhpmevent14].OF << 14);
value = value | (CSR[mhpmevent15].OF << 15);
value = value | (CSR[mhpmevent16].OF << 16);
value = value | (CSR[mhpmevent17].OF << 17);
value = value | (CSR[mhpmevent18].OF << 18);
value = value | (CSR[mhpmevent19].OF << 19);
value = value | (CSR[mhpmevent20].OF << 20);
value = value | (CSR[mhpmevent21].OF << 21);
value = value | (CSR[mhpmevent22].OF << 22);
value = value | (CSR[mhpmevent23].OF << 23);
value = value | (CSR[mhpmevent24].OF << 24);
value = value | (CSR[mhpmevent25].OF << 25);
value = value | (CSR[mhpmevent26].OF << 26);
value = value | (CSR[mhpmevent27].OF << 27);
value = value | (CSR[mhpmevent28].OF << 28);
value = value | (CSR[mhpmevent29].OF << 29);
value = value | (CSR[mhpmevent30].OF << 30);
value = value | (CSR[mhpmevent31].OF << 31);
return value & mask;