henvcfgh

most-significant 32 bits of Hypervisor Environment Configuration

The henvcfgh CSR is a 32-bit read/write register for the most-significant 32 bits of henvcfg.

Attributes

CSR Address

0x61a

Defining extension

  • allOf:

    • Sm, version >=1.12

    • H, version >= H@1.0.0

Length

32-bit

Privilege Mode

S

Format

henvcfgh format
Figure 1. henvcfgh format

Field Summary

Name Location Type Reset Value

STCE

31

RO

UNDEFINED_LEGAL

Fields

STCE

Location

henvcfgh[31]

Description

STimecmp Enable

When set, stimecmp is operational in VS-mode if menvcfg.STCE is also set.

When menvcfg.STCE is zero: * henvcfg.STCE reads-as-zero * vstimecmp access raises an IllegalInstruction exception. * hip.VSTIP reverts to its defined behavior as if Sstc is not implemented. * VS-mode timer interrupts will not be generated

+ When menvcfg.STCE is one and henvcfg.STCE is zero:

  • Accessing stimecmp in VS-mode or VU-mode (really vstimecmp) raises a VirtualInterrupt exception

  • hip.VSTIP reverts to its defined behavior as if Sstc is not implemented.

  • VS-mode timer interrupts will not be generated

Type

RO

Read-Only

Field has a hardwired value that does not change. Writes to an RO field are ignored.
Reset value

UNDEFINED_LEGAL

Software read

This CSR may return a value that is different from what is stored in hardware.

  • Pruned

  • Original

return CSR[henvcfg].sw_read()[63:32];
return CSR[henvcfg].sw_read()[63:32];