D Extension
- Implemented Version
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2.2.0
Versions
- 2.2.0
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- Ratification date
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2019-12
- Changes
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Define NaN-boxing scheme, changed definition of FMAX and FMIN
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- Implies
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F version 2.2.0
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Synopsis
The D extension adds double-precision floating-point computational instructions compliant with the IEEE 754-2008 arithmetic standard. The D extension depends on the base single-precision instruction subset F.
D Register State
The D extension widens the 32 floating-point registers, f0-f31, to
64 bits (FLEN=64 in [fprs]. The f registers can
now hold either 32-bit or 64-bit floating-point values as described
below in NaN Boxing of Narrower Values.
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FLEN can be 32, 64, or 128 depending on which of the F, D, and Q extensions are supported. There can be up to four different floating-point precisions supported, including H, F, D, and Q. |
NaN Boxing of Narrower Values
When multiple floating-point precisions are supported, then valid values of narrower n-bit types, n<FLEN, are represented in the lower n bits of an FLEN-bit NaN value, in a process termed NaN-boxing. The upper bits of a valid NaN-boxed value must be all 1s. Valid NaN-boxed n-bit values therefore appear as negative quiet NaNs (qNaNs) when viewed as any wider m-bit value, n < m ≤ FLEN. Any operation that writes a narrower result to an 'f' register must write all 1s to the uppermost FLEN-n bits to yield a legal NaN-boxedvalue.
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Software might not know the current type of data stored in a floating-point register but has to be able to save and restore the register values, hence the result of using wider operations to transfer narrower values has to be defined. A common case is for callee-saved registers, but a standard convention is also desirable for features including varargs, user-level threading libraries, virtual machine migration, and debugging. |
Floating-point n-bit transfer operations move external
values held in IEEE standard formats into and out of the f registers,
and comprise floating-point loads and stores (FLn/FSn) and floating-point move instructions (FMV.n.X/FMV.X.n). A narrower n-bit transfer, n<FLEN, into the f registers will create a valid NaN-boxed value. A narrower
n-bit transfer out of the floating-point registers will
transfer the lower n bits of the register ignoring the
upper FLEN-n bits.
Apart from transfer operations described in the previous paragraph, all other floating-point operations on narrower n-bit operations, n<FLEN, check if the input operands are correctly NaN-boxed, i.e., all upper FLEN-n bits are 1. If so, the n least-significant bits of the input are used as the input value, otherwise the input value is treated as an n-bit canonical NaN.
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Earlier versions of this document did not define the behavior of feeding the results of narrower or wider operands into an operation, except to require that wider saves and restores would preserve the value of a narrower operand. The new definition removes this implementation-specific behavior, while still accommodating both non-recoded and recoded implementations of the floating-point unit. The new definition also helps catch software errors by propagating NaNs if values are used incorrectly. Non-recoded implementations unpack and pack the operands to IEEE standard format on the input and output of every floating-point operation. The NaN-boxing cost to a non-recoded implementation is primarily in checking if the upper bits of a narrower operation represent a legal NaN-boxed value, and in writing all 1s to the upper bits of a result. Recoded implementations use a more convenient internal format to represent floating-point values, with an added exponent bit to allow all values to be held normalized. The cost to the recoded implementation is primarily the extra tagging needed to track the internal types and sign bits, but this can be done without adding new state bits by recoding NaNs internally in the exponent field. Small modifications are needed to the pipelines used to transfer values in and out of the recoded format, but the datapath and latency costs are minimal. The recoding process has to handle shifting of input subnormal values for wide operands in any case, and extracting the NaN-boxed value is a similar process to normalization except for skipping over leading-1 bits instead of skipping over leading-0 bits, allowing the datapath muxing to be shared. |
Instructions
The following instructions are added by this extension in the example_rv64_with_overlay configuration:
Floating-Point Add Double-Precision |
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Floating-Point Classify Double-Precision |
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Floating-Point Convert Long to Double-Precision |
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Floating-Point Convert Unsigned Long to Double-Precision |
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Floating-Point Convert Single-Precision to Double-Precision |
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Floating-Point Convert Word to Double-Precision |
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Floating-Point Convert Unsigned Word to Double-Precision |
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Floating-Point Convert Double-Precision to Long |
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Floating-Point Convert Double-Precision to Unsigned Long |
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Floating-Point Convert Double-Precision to Single-Precision |
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Floating-Point Convert Double-Precision to Word |
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Floating-Point Convert Double-Precision to Unsigned Word |
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Floating-Point Convert Double-Precision to Word with Modulo |
Floating-Point Divide Double-Precision |
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Floating-Point Equal Double-Precision |
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Floating-Point Load Double-Precision |
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Floating-Point Less Than or Equal Double-Precision |
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Floating-Point Less Than or Equal Quiet Double-Precision |
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Floating-Point Load Immediate Double-Precision |
Floating-Point Less Than Double-Precision |
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Floating-Point Less Than Quiet Double-Precision |
Floating-Point Multiply-Add Double-Precision |
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Floating-Point Maximum-Number Double-Precision |
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Floating-Point Maximum-Number NaN Double-Precision |
Floating-Point Minimum-Number Double-Precision |
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Floating-Point Minimum-Number NaN Double-Precision |
Floating-Point Multiply-Subtract Double-Precision |
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Floating-Point Multiply Double-Precision |
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Floating-Point Move from Integer Register to Double-Precision Register |
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Floating-Point Move from Double-Precision Register to Integer Register |
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Floating-Point Move High Half from Double-Precision Register to Integer Register |
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Floating-Point Move Pair from Integer Registers to Double-Precision Register |
Floating-Point Negate-Multiply-Add Double-Precision |
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Floating-Point Negate-Multiply-Subtract Double-Precision |
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Floating-Point Round Double-Precision |
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Floating-Point Round-to-Integer Inexact Double-Precision |
Floating-Point Store Double-Precision |
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Floating-Point Sign-Inject Double-Precision |
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Floating-Point Sign-Inject Negate Double-Precision |
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Floating-Point Sign-Inject XOR Double-Precision |
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Floating-Point Square Root Double-Precision |
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Floating-Point Subtract Double-Precision |
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Floating-Point Add Single-Precision |
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Floating-Point Classify Single-Precision |
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Floating-Point Convert Single-Precision to Long |
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Floating-Point Convert Single-Precision to Unsigned Long |
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Floating-Point Convert Long to Single-Precision |
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Floating-Point Convert Unsigned Long to Single-Precision |
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Floating-Point Convert Word to Single-Precision |
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Floating-Point Convert Unsigned Word to Single-Precision |
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Floating-Point Convert Single-Precision to Word |
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Floating-Point Convert Single-Precision to Unsigned Word |
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Floating-Point Divide Single-Precision |
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Floating-Point Equal Single-Precision |
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Floating-Point Less Than or Equal Single-Precision |
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Floating-Point Less Than Single-Precision |
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Floating-Point Load Single-Precision |
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Floating-Point Multiply-Add Single-Precision |
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Floating-Point Maximum-Number Single-Precision |
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Floating-Point Minimum-Number Single-Precision |
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Floating-Point Multiply-Subtract Single-Precision |
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Floating-Point Multiply Single-Precision |
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Floating-Point Move Single-Precision Word from Integer Register |
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Floating-Point Move Single-Precision Word to Integer Register |
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Floating-Point Negate-Multiply-Add Single-Precision |
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Floating-Point Negate-Multiply-Subtract Single-Precision |
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Floating-Point Sign-Inject Single-Precision |
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Floating-Point Sign-Inject Negate Single-Precision |
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Floating-Point Sign-Inject XOR Single-Precision |
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Floating-Point Square Root Single-Precision |
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Floating-Point Subtract Single-Precision |
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Floating-Point Store Single-Precision |
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Load double-precision |
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Load doubleword into floating-point register from stack |
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Store double-precision |
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Store double-precision value to stack |
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Load single-precision |
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Load word into floating-point register from stack |
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Store single-precision |
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Store single-precision value to stack |
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No synopsis available |
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Floating-point Convert Double-precision to Half-precision |