misa

Machine ISA Control

Reports the XLEN and "major" extensions supported by the ISA.

Attributes

CSR Address

0x301

Defining extension

Sm, version >= Sm@1.11.0

Length

64-bit

Privilege Mode

M

Format

misa format
Figure 1. misa format

Field Summary

Name Location Type Reset Value

MXL

63:62

RO

2

A

0

[when,"implemented?(ExtensionName::A) && MUTABLE_MISA_A"] RW

[when,"!implemented?(ExtensionName::A) && MUTABLE_MISA_A"] RO

UNDEFINED_LEGAL

B

1

[when,"implemented?(ExtensionName::B) && MUTABLE_MISA_B"] RW

[when,"!implemented?(ExtensionName::B) && MUTABLE_MISA_B"] RO

UNDEFINED_LEGAL

C

2

[when,"implemented?(ExtensionName::C) && MUTABLE_MISA_C"] RW

[when,"!implemented?(ExtensionName::C) && MUTABLE_MISA_C"] RO

UNDEFINED_LEGAL

D

3

[when,"implemented?(ExtensionName::D) && MUTABLE_MISA_D"] RW

[when,"!implemented?(ExtensionName::D) && MUTABLE_MISA_D"] RO

UNDEFINED_LEGAL

F

5

[when,"implemented?(ExtensionName::F) && MUTABLE_MISA_F"] RW

[when,"!implemented?(ExtensionName::F) && MUTABLE_MISA_F"] RO

UNDEFINED_LEGAL

G

6

[when,"(((implemented?(ExtensionName::A) && MUTABLE_MISA_A

implemented?(ExtensionName::M) && MUTABLE_MISA_M)

implemented?(ExtensionName::F) && MUTABLE_MISA_F)

implemented?(ExtensionName::D) && MUTABLE_MISA_D)"] RO-H [when,"!(((implemented?(ExtensionName::A) && MUTABLE_MISA_A

implemented?(ExtensionName::M) && MUTABLE_MISA_M)

implemented?(ExtensionName::F) && MUTABLE_MISA_F)

implemented?(ExtensionName::D) && MUTABLE_MISA_D)"] RO

UNDEFINED_LEGAL

H

7

[when,"implemented?(ExtensionName::H) && MUTABLE_MISA_H"] RW

[when,"!implemented?(ExtensionName::H) && MUTABLE_MISA_H"] RO

UNDEFINED_LEGAL

I

8

RO

1

M

12

[when,"implemented?(ExtensionName::M) && MUTABLE_MISA_M"] RW

[when,"!implemented?(ExtensionName::M) && MUTABLE_MISA_M"] RO

UNDEFINED_LEGAL

S

18

[when,"implemented?(ExtensionName::S) && MUTABLE_MISA_S"] RW

[when,"!implemented?(ExtensionName::S) && MUTABLE_MISA_S"] RO

UNDEFINED_LEGAL

U

20

[when,"implemented?(ExtensionName::U) && MUTABLE_MISA_U"] RW

[when,"!implemented?(ExtensionName::U) && MUTABLE_MISA_U"] RO

UNDEFINED_LEGAL

V

21

[when,"implemented?(ExtensionName::V) && MUTABLE_MISA_V"] RW

[when,"!implemented?(ExtensionName::V) && MUTABLE_MISA_V"] RO

UNDEFINED_LEGAL

Fields

MXL

Location

misa[63:62]

Description

XLEN in M-mode.

Type

RO

Read-Only

Field has a hardwired value that does not change. Writes to an RO field are ignored.
Reset value

2

A

Location

misa[0]

Description

Indicates support for the A (atomic) extension.

Writing 0 to this field will cause all atomic instructions to raise an IllegalInstruction exception.

Type
Reset value

UNDEFINED_LEGAL

B

Location

misa[1]

Description

Indicates support for the B (bitmanip) extension.

Writing 0 to this field will cause all bitmanip instructions to raise an IllegalInstruction exception.

Type
Reset value

UNDEFINED_LEGAL

C

Location

misa[2]

Description

Indicates support for the C (compressed) extension.

Writing 0 to this field will cause all compressed instructions to raise an IllegalInstruction exception. Additionally, IALIGN becomes 32.

Type
Reset value

UNDEFINED_LEGAL

D

Location

misa[3]

Description

Indicates support for the D (double precision float) extension.

Writing 0 to this field will cause all double-precision floating point instructions to raise an IllegalInstruction exception.

+ Additionally, the upper 32-bits of the f registers will read as zero.

Type
Reset value

UNDEFINED_LEGAL

F

Location

misa[5]

Description

Indicates support for the F (single precision float) extension.

Writing 0 to this field will cause all floating point (single and double precision) instructions to raise an IllegalInstruction exception.

+ Writing 0 to this field with misa.D set will result in UNDEFINED behavior.

Type
Reset value

UNDEFINED_LEGAL

Software write

This field has special behavior when written by software (e.g., through csrrw).

When software tries to write csr_value, the field will be written with the return value of the function below.

if (csr_value.F == 0 && csr_value.D == 1) {
  return UNDEFINED_LEGAL_DETERMINISTIC;
}
return csr_value.F;

G

Location

misa[6]

Description

Indicates support for all of the following extensions: I, A, M, F, D.

Type
Reset value

UNDEFINED_LEGAL

H

Location

misa[7]

Description

Indicates support for the H (hypervisor) extension.

Writing 0 to this field will cause all attempts to enter VS- or VU- mode, execute a hypervisor instruction, or access a hypervisor CSR to raise an IllegalInstruction fault.

Type
Reset value

UNDEFINED_LEGAL

I

Location

misa[8]

Description

Indicates support for the I (base) extension.

Type

RO

Read-Only

Field has a hardwired value that does not change. Writes to an RO field are ignored.
Reset value

1

M

Location

misa[12]

Description

Indicates support for the M (integer multiply/divide) extension.

Writing 0 to this field will cause all attempts to execute an integer multiply or divide instruction to raise an IllegalInstruction exception.

Type
Reset value

UNDEFINED_LEGAL

S

Location

misa[18]

Description

Indicates support for the S (supervisor mode) extension.

Writing 0 to this field will cause all attempts to enter S-mode or access S-mode state to raise an exception.

Type
Reset value

UNDEFINED_LEGAL

U

Location

misa[20]

Description

Indicates support for the U (user mode) extension.

Writing 0 to this field will cause all attempts to enter U-mode to raise an exception.

Type
Reset value

UNDEFINED_LEGAL

V

Location

misa[21]

Description

Indicates support for the V (vector) extension.

Writing 0 to this field will cause all attempts to execute a vector instruction to raise an IllegalInstruction trap.

Type
Reset value

UNDEFINED_LEGAL

Software read

This CSR may return a value that is different from what is stored in hardware.

  • Pruned

  • Original

return misa.MXL << (xlen() - 2 | (misa.V << 21) | (misa.U << 20) | (misa.S << 18) | (misa.M << 12) | (misa.I << 7) | (misa.H << 6) | ((misa.A & misa.M & misa.F & misa.D) << 5) | (misa.F << 4) | (misa.D << 3) | (misa.C << 2) | (misa.B << 1) | misa.A);
return misa.MXL << (xlen() - 2 | (misa.V << 21) | (misa.U << 20) | (misa.S << 18) | (misa.Q << 16) | (misa.M << 12) | (misa.I << 7) | (misa.H << 6) | ((misa.A & misa.M & misa.F & misa.D) << 5) | (misa.F << 4) | (misa.D << 3) | (misa.C << 2) | (misa.B << 1) | misa.A);