divw
Signed 32-bit division
This instruction is defined by:
Synopsis
Divide the lower 32-bits of register rs1 by the lower 32-bits of register rs2, and store the sign-extended result in rd.
The remainder is discarded.
Division by zero will put -1 into rd.
Division resulting in signed overflow (when most negative number is divided by -1) will put the most negative number into rd;
Decode Variables
Bits<5> rs2 = $encoding[24:20];
Bits<5> rs1 = $encoding[19:15];
Bits<5> rd = $encoding[11:7];Execution
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Pruned, XLEN == 64
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Original
if ((%%LINK%csr_field;misa.M;CSR[misa].M%% == 1'b0)) {
%%LINK%func;raise;raise%%(ExceptionCode::IllegalInstruction, %%LINK%func;mode;mode%%(), $encoding);
}
Bits<32> src1 = X[rs1][31:0];
Bits<32> src2 = X[rs2][31:0];
if (src2 == 0) {
X[rd] = {MXLEN{1'b1}};
} else if ((src1 == {33'b1, 31'b0}) && (src2 == 32'b1)) {
X[rd] = {33'b1, 31'b0};
} else {
Bits<32> result = $signed(src1) / $signed(src2);
Bits<1> sign_bit = result[31];
X[rd] = {{32{sign_bit}}, result};
}if (%%LINK%func;implemented?;implemented?%%(ExtensionName::M) && (%%LINK%csr_field;misa.M;CSR[misa].M%% == 1'b0)) {
%%LINK%func;raise;raise%%(ExceptionCode::IllegalInstruction, %%LINK%func;mode;mode%%(), $encoding);
}
Bits<32> src1 = X[rs1][31:0];
Bits<32> src2 = X[rs2][31:0];
if (src2 == 0) {
X[rd] = {MXLEN{1'b1}};
} else if ((src1 == {33'b1, 31'b0}) && (src2 == 32'b1)) {
X[rd] = {33'b1, 31'b0};
} else {
Bits<32> result = $signed(src1) / $signed(src2);
Bits<1> sign_bit = result[31];
X[rd] = {{32{sign_bit}}, result};
}