csrrsi
Atomic Read and Set Bits in CSR with Immediate
This instruction is defined by:
Synopsis
The CSRRSI variant is similar to CSRRS, except this updates the CSR using an XLEN-bit value obtained
by zero-extending a 5-bit unsigned immediate (uimm[4:0]) field encoded in the rs1 field instead of a
value from an integer register. For CSRRSI, if the uimm[4:0] field is zero, then this instruction
will not write to the CSR, and shall not cause any of the side effects that might otherwise occur on
a CSR write, nor raise illegal-instruction exceptions on accesses to read-only CSRs. The CSRRSI will
always read the CSR and cause any read side effects regardless of rd and rs1 fields.
Decode Variables
Bits<12> csr = $encoding[31:20];
Bits<5> uimm = $encoding[19:15];
Bits<5> xd = $encoding[11:7];Execution
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Pruned, XLEN == 64
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Original
Boolean will_write = uimm != 0;
Csr csr_handle = direct_csr_lookup(csr);
if (csr_handle.valid == false) {
unimplemented_csr($encoding);
} else if (!compatible_mode?(csr_handle.mode, mode())) {
raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
} else if (will_write && csr_handle.writable == false) {
raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
}
XReg initial_csr_value = csr_sw_read(csr_handle);
if (will_write) {
XReg mask = uimm;
csr_sw_write(csr_handle, initial_csr_value | mask);
}
X[xd] = initial_csr_value;Boolean will_write = uimm != 0;
Csr csr_handle = direct_csr_lookup(csr);
if (csr_handle.valid == false) {
unimplemented_csr($encoding);
} else if (!compatible_mode?(csr_handle.mode, mode())) {
raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
} else if (will_write && csr_handle.writable == false) {
raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
}
XReg initial_csr_value = csr_sw_read(csr_handle);
if (will_write) {
XReg mask = uimm;
csr_sw_write(csr_handle, initial_csr_value | mask);
}
X[xd] = initial_csr_value;