pmpcfg15

PMP Configuration Register 15

PMP entry configuration

Attributes

CSR Address

0x3af

Defining extension

  • Smpmp, version >= Smpmp@1.11.0

Length

64-bit

Privilege Mode

M

Format

pmpcfg15 format
Figure 1. pmpcfg15 format

Field Summary

Name Location Type Reset Value

pmp60cfg

7:0

RO

0

pmp61cfg

15:8

RO

0

pmp62cfg

23:16

RO

0

pmp63cfg

31:24

RO

0

Fields

pmp60cfg

Location

pmpcfg15[7:0]

Description

PMP configuration for entry 60

The bits are as follows:

Name

Location

Description +

L

7

Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.

-

6:5

Reserved Writes shall be ignored.

A

4:3

Address matching mode. One of:

+ [when="PMP_GRANULARITY < 2"] * OFF (0) - Null region (disabled) * TOR (1) - Top of range * NA4 (2) - Naturally aligned four-byte region * NAPOT (3) - Naturally aligned power of two

+ [when="PMP_GRANULARITY >= 2"] * OFF (0) - Null region (disabled) * TOR (1) - Top of range * NAPOT (3) - Naturally aligned power of two

+

Naturally aligned four-byte region, NA4 (2), is not valid (not needed when the PMP granularity is larger than 4 bytes).

+

X

2

When clear, instruction fetches cause an Access Fault for the matching region and privilege mode.

W

1

When clear, stores and AMOs cause an Access Fault for the matching region and privilege mode.

R

0

When clear, loads cause an Access Fault for the matching region and privilege mode.

The combination of R = 0, W = 1 is reserved.

Type

RO

Read-Only

Field has a hardwired value that does not change. Writes to an RO field are ignored.

Reset value

0

Software write

This field has special behavior when written by software (e.g., through csrrw).

When software tries to write csr_value, the field will be written with the return value of the function below.

if ((%%LINK%csr_field;pmpcfg15.pmp60cfg;CSR[pmpcfg15].pmp60cfg%%) == 0) {
  if (! {
    if (csr_value.pmp60cfg & 0x18) != 0x10 {
      return csr_value.pmp60cfg;
    }
  }
}
return %%LINK%csr_field;pmpcfg15.pmp60cfg;CSR[pmpcfg15].pmp60cfg%%;

pmp61cfg

Location

pmpcfg15[15:8]

Description

PMP configuration for entry 61

The bits are as follows:

Name

Location

Description +

L

15

Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.

-

14:13

Reserved Writes shall be ignored.

A

12:11

Address matching mode. One of:

+ [when="PMP_GRANULARITY < 2"] * OFF (0) - Null region (disabled) * TOR (1) - Top of range * NA4 (2) - Naturally aligned four-byte region * NAPOT (3) - Naturally aligned power of two

+ [when="PMP_GRANULARITY >= 2"] * OFF (0) - Null region (disabled) * TOR (1) - Top of range * NAPOT (3) - Naturally aligned power of two

+

Naturally aligned four-byte region, NA4 (2), is not valid (not needed when the PMP granularity is larger than 4 bytes).

+

X

10

When clear, instruction fetches cause an Access Fault for the matching region and privilege mode.

W

9

When clear, stores and AMOs cause an Access Fault for the matching region and privilege mode.

R

8

When clear, loads cause an Access Fault for the matching region and privilege mode.

The combination of R = 0, W = 1 is reserved.

Type

RO

Read-Only

Field has a hardwired value that does not change. Writes to an RO field are ignored.

Reset value

0

Software write

This field has special behavior when written by software (e.g., through csrrw).

When software tries to write csr_value, the field will be written with the return value of the function below.

if ((%%LINK%csr_field;pmpcfg15.pmp61cfg;CSR[pmpcfg15].pmp61cfg%%) == 0) {
  if (! {
    if (csr_value.pmp61cfg & 0x18) != 0x10 {
      return csr_value.pmp61cfg;
    }
  }
}
return %%LINK%csr_field;pmpcfg15.pmp61cfg;CSR[pmpcfg15].pmp61cfg%%;

pmp62cfg

Location

pmpcfg15[23:16]

Description

PMP configuration for entry 62

The bits are as follows:

Name

Location

Description +

L

23

Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.

-

22:21

Reserved Writes shall be ignored.

A

20:19

Address matching mode. One of:

+ [when="PMP_GRANULARITY < 2"] * OFF (0) - Null region (disabled) * TOR (1) - Top of range * NA4 (2) - Naturally aligned four-byte region * NAPOT (3) - Naturally aligned power of two

+ [when="PMP_GRANULARITY >= 2"] * OFF (0) - Null region (disabled) * TOR (1) - Top of range * NAPOT (3) - Naturally aligned power of two

+

Naturally aligned four-byte region, NA4 (2), is not valid (not needed when the PMP granularity is larger than 4 bytes).

+

X

18

When clear, instruction fetches cause an Access Fault for the matching region and privilege mode.

W

17

When clear, stores and AMOs cause an Access Fault for the matching region and privilege mode.

R

16

When clear, loads cause an Access Fault for the matching region and privilege mode.

The combination of R = 0, W = 1 is reserved.

Type

RO

Read-Only

Field has a hardwired value that does not change. Writes to an RO field are ignored.

Reset value

0

Software write

This field has special behavior when written by software (e.g., through csrrw).

When software tries to write csr_value, the field will be written with the return value of the function below.

if ((%%LINK%csr_field;pmpcfg15.pmp62cfg;CSR[pmpcfg15].pmp62cfg%%) == 0) {
  if (! {
    if (csr_value.pmp62cfg & 0x18) != 0x10 {
      return csr_value.pmp62cfg;
    }
  }
}
return %%LINK%csr_field;pmpcfg15.pmp62cfg;CSR[pmpcfg15].pmp62cfg%%;

pmp63cfg

Location

pmpcfg15[31:24]

Description

PMP configuration for entry 63

The bits are as follows:

Name

Location

Description +

L

31

Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.

-

30:29

Reserved Writes shall be ignored.

A

28:27

Address matching mode. One of:

+ [when="PMP_GRANULARITY < 2"] * OFF (0) - Null region (disabled) * TOR (1) - Top of range * NA4 (2) - Naturally aligned four-byte region * NAPOT (3) - Naturally aligned power of two

+ [when="PMP_GRANULARITY >= 2"] * OFF (0) - Null region (disabled) * TOR (1) - Top of range * NAPOT (3) - Naturally aligned power of two

+

Naturally aligned four-byte region, NA4 (2), is not valid (not needed when the PMP granularity is larger than 4 bytes).

+

X

26

When clear, instruction fetches cause an Access Fault for the matching region and privilege mode.

W

25

When clear, stores and AMOs cause an Access Fault for the matching region and privilege mode.

R

24

When clear, loads cause an Access Fault for the matching region and privilege mode.

The combination of R = 0, W = 1 is reserved.

Type

RO

Read-Only

Field has a hardwired value that does not change. Writes to an RO field are ignored.

Reset value

0

Software write

This field has special behavior when written by software (e.g., through csrrw).

When software tries to write csr_value, the field will be written with the return value of the function below.

if ((%%LINK%csr_field;pmpcfg15.pmp63cfg;CSR[pmpcfg15].pmp63cfg%%) == 0) {
  if (! {
    if (csr_value.pmp63cfg & 0x18) != 0x10 {
      return csr_value.pmp63cfg;
    }
  }
}
return %%LINK%csr_field;pmpcfg15.pmp63cfg;CSR[pmpcfg15].pmp63cfg%%;