mstatus

Machine Status

The mstatus register tracks and controls the hart’s current operating state.

Attributes

CSR Address	0x300
Defining extension	Sm
Length	64-bit
Privilege Mode	M

CSR Address

0x300

Defining extension

Length

64-bit

Privilege Mode

Format

Figure 1. mstatus format

Field Summary

Name Location Type Reset Value

Name	Location	Type	Reset Value
`SD`	63	RO-H	UNDEFINED_LEGAL
`MPV`	39	RW-H	UNDEFINED_LEGAL
`GVA`	38	RW-H	0
`MBE`	37	RO	0
`SBE`	36	RO	0
`SXL`	35:34	[when,"implemented?(ExtensionName::S) && $array_size(SXLEN) > 1"] RW [when,"!implemented?(ExtensionName::S) && $array_size(SXLEN) > 1"] RO	UNDEFINED_LEGAL
`UXL`	33:32	[when,"$array_size(UXLEN) > 1"] RW [when,"$array_size(UXLEN) ⇐ 1"] RO	UNDEFINED_LEGAL
`TSR`	22	RW	UNDEFINED_LEGAL
`TW`	21	RW	UNDEFINED_LEGAL
`TVM`	20	[when,"(CSR[misa].S == 1’b0)"] RO [when,"(CSR[misa].S != 1’b0)"] RW	UNDEFINED_LEGAL
`MXR`	19	RW	UNDEFINED_LEGAL
`SUM`	18	RW	UNDEFINED_LEGAL
`MPRV`	17	[when,"CSR[misa].U == 1’b1"] RW-H [when,"CSR[misa].U != 1’b1"] RO	0
`XS`	16:15	RO	0
`FS`	14:13	[when,"(implemented?(ExtensionName::F) && ((!MISA_CSR_IMPLEMENTED
(CSR[misa].F == 1’b1))))"] RW-H [when,"MISA_CSR_IMPLEMENTED && ((CSR[misa].S == 1’b0) && CSR[misa].F == 1’b0)"] RO [when,"else"] [when,"$array_size(MSTATUS_FS_LEGAL_VALUES) == 1"] RO [when,"$array_size(MSTATUS_FS_LEGAL_VALUES) != 1"] RW	UNDEFINED_LEGAL	`MPP`	12:11
RW-H	3	`VS`	10:9
[when,"(implemented?(ExtensionName::V) && ((!MISA_CSR_IMPLEMENTED		(CSR[misa].V == 1’b1))))"] RW-H [when,"MISA_CSR_IMPLEMENTED && ((CSR[misa].S == 1’b0) && CSR[misa].V == 1’b0)"] RO [when,"else"] [when,"$array_size(MSTATUS_VS_LEGAL_VALUES) == 1"] RO [when,"$array_size(MSTATUS_VS_LEGAL_VALUES) != 1"] RW	UNDEFINED_LEGAL
`SPP`	8	RW-H	UNDEFINED_LEGAL
`MPIE`	7	RW-H	UNDEFINED_LEGAL
`UBE`	6	RO	0
`SPIE`	5	[when,"CSR[misa].S == 1’b1"] RW-H [when,"CSR[misa].S != 1’b1"] RO	UNDEFINED_LEGAL
`MIE`	3	RW-H	0
`SIE`	1	[when,"CSR[misa].S == 1’b1"] RW-H [when,"CSR[misa].S != 1’b1"] RO	UNDEFINED_LEGAL

SD

RO-H

UNDEFINED_LEGAL

MPV

RW-H

UNDEFINED_LEGAL

GVA

RW-H

MBE

SBE

SXL

35:34

[when,"implemented?(ExtensionName::S) && $array_size(SXLEN) > 1"] RW

[when,"!implemented?(ExtensionName::S) && $array_size(SXLEN) > 1"] RO

UNDEFINED_LEGAL

UXL

33:32

[when,"$array_size(UXLEN) > 1"] RW

[when,"$array_size(UXLEN) ⇐ 1"] RO

UNDEFINED_LEGAL

TSR

UNDEFINED_LEGAL

TW

UNDEFINED_LEGAL

TVM

[when,"(CSR[misa].S == 1’b0)"] RO [when,"(CSR[misa].S != 1’b0)"] RW

UNDEFINED_LEGAL

MXR

UNDEFINED_LEGAL

SUM

UNDEFINED_LEGAL

MPRV

[when,"CSR[misa].U == 1’b1"] RW-H

[when,"CSR[misa].U != 1’b1"] RO

XS

16:15

FS

14:13

[when,"(implemented?(ExtensionName::F) && ((!MISA_CSR_IMPLEMENTED

(CSR[misa].F == 1’b1))))"] RW-H [when,"MISA_CSR_IMPLEMENTED && ((CSR[misa].S == 1’b0) && CSR[misa].F == 1’b0)"] RO [when,"else"] [when,"$array_size(MSTATUS_FS_LEGAL_VALUES) == 1"] RO

[when,"$array_size(MSTATUS_FS_LEGAL_VALUES) != 1"] RW

UNDEFINED_LEGAL

MPP

12:11

RW-H

VS

10:9

[when,"(implemented?(ExtensionName::V) && ((!MISA_CSR_IMPLEMENTED

(CSR[misa].V == 1’b1))))"] RW-H [when,"MISA_CSR_IMPLEMENTED && ((CSR[misa].S == 1’b0) && CSR[misa].V == 1’b0)"] RO [when,"else"] [when,"$array_size(MSTATUS_VS_LEGAL_VALUES) == 1"] RO

[when,"$array_size(MSTATUS_VS_LEGAL_VALUES) != 1"] RW

UNDEFINED_LEGAL

SPP

RW-H

UNDEFINED_LEGAL

MPIE

RW-H

UNDEFINED_LEGAL

UBE

SPIE

[when,"CSR[misa].S == 1’b1"] RW-H

[when,"CSR[misa].S != 1’b1"] RO

UNDEFINED_LEGAL

MIE

RW-H

SIE

[when,"CSR[misa].S == 1’b1"] RW-H

[when,"CSR[misa].S != 1’b1"] RO

UNDEFINED_LEGAL

Fields

`SD`

Location: mstatus[63]
Description: Read-only bit that summarizes whether either the FS, XS, or VS fields signal the presence of some dirty state.
Type

RO-H	Read-Only with Hardware update Writes are ignored. Reads reflect a value dynamically generated by hardware.

Reset value: UNDEFINED_LEGAL

`MPV`

Location: mstatus[39]
Description: Written with the prior virtualization mode when entering M-mode from an exception/interrupt. When returning via an MRET instruction, the virtualization mode becomes the value of MPV unless MPP=3, in which case the virtualization mode is always 0. Can also be written by software.
Type

RW-H	Read-Write with Hardware update Field is writable by software. Any value that fits in the field is acceptable. Hardware also updates the field without an explicit software write.

Reset value: UNDEFINED_LEGAL

`GVA`

Location: mstatus[38]
Description: When a trap is taken and a guest virtual address is written into mtval, GVA is set. When a trap is taken and a guest virtual address is written into mtval, GVA is cleared.
Type

RW-H	Read-Write with Hardware update Field is writable by software. Any value that fits in the field is acceptable. Hardware also updates the field without an explicit software write.

Reset value: 0

`MBE`

Location: mstatus[37]
Description: Controls the endianness of data M-mode (0 = little, 1 = big). Instructions are always little endian, regardless of the data setting.

Since the CPU does not support big endian, this is hardwired to 0.

Since the CPU does not support little endian, this is hardwired to 1.
Type

RO	Read-Only Field has a hardwired value that does not change. Writes to an RO field are ignored.

Reset value: 0

`SBE`

Location: mstatus[36]
Description: Controls the endianness of S-mode (0 = little, 1 = big). Instructions are always little endian, regardless of the data setting.

Since the CPU does not support big endian, this is hardwired to 0.

Since the CPU does not support little endian, this is hardwired to 1.
Type

RO	Read-Only Field has a hardwired value that does not change. Writes to an RO field are ignored.

Reset value: 0

`SXL`

Location: mstatus[35:34]
Description: Sets the effective XLEN for S-mode (0 = 32-bit, 1 = 64-bit, 2 = 128-bit [reserved]).

Since the CPU only supports SXLEN==32, this is hardwired to 1.

Since the CPU only supports SXLEN==64, this is hardwired to 2.

It is not valid to have SXLEN less than UXLEN.

+ It is UNDEFINED_LEGAL what will happen if a software sets mstatus.SXL to be greater than mstatus.UXL.

+ It is UNDEFINED_LEGAL to set the MSB of SXL.

Type

Reset value

UNDEFINED_LEGAL

Software write

This field has special behavior when written by software (e.g., through csrrw).

When software tries to write csr_value, the field will be written with the return value of the function below.

if (csr_value.SXL < csr_value.UXL) {
  return CSR[mstatus].SXL;
} else if (csr_value.SXL < 1 || csr_value.SXL > 2) {
  return CSR[mstatus].SXL;
} else {
  return csr_value.SXL;
}

`UXL`

Location: mstatus[33:32]
Description: U-mode XLEN.

Sets the effective XLEN for U-mode (1 = 32-bit, 2 = 64-bit, 3 = 128-bit [reserved]).

Since the CPU only supports UXLEN==32, this is hardwired to 1.

Since the CPU only supports UXLEN==64, this is hardwired to 2.

It is not valid to have SXLEN less than UXLEN.

+ It is UNDEFINED_LEGAL what will happen if a software sets mstatus.SXL to be greater than mstatus.UXL.

+ It is UNDEFINED_LEGAL to set the MSB of UXL.

Type

Reset value

UNDEFINED_LEGAL

Software write

This field has special behavior when written by software (e.g., through csrrw).

When software tries to write csr_value, the field will be written with the return value of the function below.

if (csr_value.SXL < csr_value.UXL) {
  return CSR[mstatus].UXL;
} else if (csr_value.UXL < 1 || csr_value.UXL > 2) {
  return CSR[mstatus].UXL;
} else {
  return csr_value.UXL;
}

`TSR`

Location: mstatus[22]
Description: When 1, attempts to execute the sret instruction while executing in HS/S-mode will raise an Illegal Instruction exception.

Does not affect the behavior of sret in VS_mode (see hstatus.VTSR).
Type

RW	Read-Write Field is writable by software. Any value that fits in the field is acceptable and shall be retained for subsequent reads.

Reset value: UNDEFINED_LEGAL

`TW`

Location: mstatus[21]
Description: When 1, the WFI instruction will raise an Illegal Instruction trap after an implementaion-defined wait period when executed in a mode other than M-mode.

When 0, the wfi instruction is permitted to wait forever in (H)S-mode but must trap after an implementation-defined wait period in U-mode.
Type

RW	Read-Write Field is writable by software. Any value that fits in the field is acceptable and shall be retained for subsequent reads.

Reset value: UNDEFINED_LEGAL

`TVM`

Location

mstatus[20]

Description

When 1, an Illegal Instruction trap occurs when

writing the satp CSR, executing an sfence.vma, or executing an sinval.vma while in (H)S-mode (but not VS-mode)
writing the hgtap CSR, executing an hfence.gvma, or executing an hinval.gvma while in HS-mode

Notably, mstatus.TVM does not cause

*hfence.vvma, sfence.w.inval, or sfence.inval.ir to trap.
Any additional traps in VS-mode (controlled via hstatus.VTVM instead).

Type

Reset value

UNDEFINED_LEGAL

Software write

This field has special behavior when written by software (e.g., through csrrw).

When software tries to write csr_value, the field will be written with the return value of the function below.

if (CSR[misa].S == 1'b0) {
  return 0;
} else {
  return csr_value.TVM;
}

`MXR`

Location: mstatus[19]
Description: When 1, loads from pages marked readable or executable are allowed. When 0, loads from pages marked executable raise a Page Fault exception.
Type

RW	Read-Write Field is writable by software. Any value that fits in the field is acceptable and shall be retained for subsequent reads.

Reset value: UNDEFINED_LEGAL

`SUM`

Location: mstatus[18]
Description: When 0, an S-mode read or an M-mode read with mstatus.MPRV=1 and mstatus.MPP=01 to a 'U' (user) page will cause an ILLEGAL INSTRUCTION exception.
Type

RW	Read-Write Field is writable by software. Any value that fits in the field is acceptable and shall be retained for subsequent reads.

Reset value: UNDEFINED_LEGAL

`MPRV`

Location: mstatus[17]
Description: When 1, loads and stores behave as if the current virtualization mode:privilege level was mstatus.MPV:mstatus.MPP.

mstatus.MPRV is cleared on any exception return (mret or sret instruction, regardless of the trap handler privilege mode).
Type

Reset value: 0

`XS`

Location: mstatus[16:15]
Description: Summarizes the current state of any custom extension state. Either 0 - Off, 1 - Initial, 2 - Clean, 3 - Dirty. Since there are no custom extensions in the base spec, this field is read-only 0.
Type

RO	Read-Only Field has a hardwired value that does not change. Writes to an RO field are ignored.

Reset value: 0

`FS`

Location: mstatus[14:13]
Description: When 0, floating point instructions (from F and D extensions) are disabled, and cause ILLEGAL INSTRUCTION exceptions. When a floating point register, or the fCSR register is written, FS obtains the value 3. Values 1 and 2 are valid write values for software, but are not interpreted by hardware other than to possibly enable a previously-disabled floating point unit.
Type

Reset value

UNDEFINED_LEGAL

Software write

This field has special behavior when written by software (e.g., through csrrw).

When software tries to write csr_value, the field will be written with the return value of the function below.

if ((CSR[misa].S == 1'b0) && (CSR[misa].F == 1'b0)) {
  return 0;
}
return $array_includes?(MSTATUS_FS_LEGAL_VALUES, csr_value.FS) ? csr_value.FS : UNDEFINED_LEGAL_DETERMINISTIC;

`MPP`

Location

mstatus[12:11]

Description

Written by hardware in two cases:

Written with the prior nominal privilege level when entering M-mode from an exception/interrupt.
Written with 0 when executing an mret instruction to return from an exception in M-mode.

Can also be written by software without immediate side-effect.

Affects execution in two cases:
On a return from an exception from M-mode, the machine will enter the privilege level stored in MPP before clearing the field.
When mstatus.MPRV is set, loads and stores behave as if the current privilege level were MPP.

Type

RW-H	Read-Write with Hardware update Field is writable by software. Any value that fits in the field is acceptable. Hardware also updates the field without an explicit software write.

Reset value

Software write

This field has special behavior when written by software (e.g., through csrrw).

When software tries to write csr_value, the field will be written with the return value of the function below.

if (false) {
  return UNDEFINED_LEGAL_DETERMINISTIC;
} else if (false) {
  return UNDEFINED_LEGAL_DETERMINISTIC;
} else if (csr_value.MPP == 2'b10) {
  return UNDEFINED_LEGAL_DETERMINISTIC;
} else {
  return csr_value.MPP;
}

`VS`

Location: mstatus[10:9]
Description: When 0, vector instructions (from the V extension) are disabled, and cause ILLEGAL INSTRUCTION exceptions. When a vector register or vector CSR is written, VS obtains the value 3. Values 1 and 2 are valid write values for software, but are not interpreted by hardware other than to possibly enable a previously-disabled vector unit.
Type

Reset value

UNDEFINED_LEGAL

Software write

This field has special behavior when written by software (e.g., through csrrw).

When software tries to write csr_value, the field will be written with the return value of the function below.

if (CSR[misa].V == 1'b1) {
  return $array_includes?(MSTATUS_VS_LEGAL_VALUES, csr_value.VS) ? csr_value.VS : UNDEFINED_LEGAL_DETERMINISTIC;
} else {
  return $array_includes?(MSTATUS_VS_LEGAL_VALUES, csr_value.VS) ? csr_value.VS : UNDEFINED_LEGAL_DETERMINISTIC;
}

`SPP`

Location

mstatus[8]

Description

Written by hardware in two cases:

Written with the prior nominal privilege level when entering (H)S-mode from an exception/interrupt.
Written with 0 when executing an sret instruction to return from an exception in (H)S-mode or (unlikely) M-mode.

Can also be written by software without immediate side-effect.

Affects execution in one case:
On a return from an exception using the sret instruction in (H)S-mode or (unlikely) M-mode, the machine will enter the privilege level stored in SPP before clearing the field.

Notably, mstatus.SPP does not affect exception return in VS-mode (see vsstatus.SPP).

Type

RW-H	Read-Write with Hardware update Field is writable by software. Any value that fits in the field is acceptable. Hardware also updates the field without an explicit software write.

Reset value

UNDEFINED_LEGAL

Software write

This field has special behavior when written by software (e.g., through csrrw).

When software tries to write csr_value, the field will be written with the return value of the function below.

if (csr_value.SPP == 2'b10) {
  return UNDEFINED_LEGAL_DETERMINISTIC;
} else {
  return csr_value.SPP;
}

`MPIE`

Location

mstatus[7]

Description

Written by hardware in two cases:

Written with prior value of mstatus.MIE when entering M-mode from an exception/interrupt.
Written with the value 1 when returning from an exception in M-mode (via the mret instruction).

Can also be written by software without immediate side effect.

Other than serving as a record of nested traps as described above, mstatus.MPIE does not affect execution.

Type

RW-H	Read-Write with Hardware update Field is writable by software. Any value that fits in the field is acceptable. Hardware also updates the field without an explicit software write.

Reset value: UNDEFINED_LEGAL

`UBE`

Location: mstatus[6]
Description: Controls the endianness of U-mode (0 = little, 1 = big). Instructions are always little endian, regardless of the data setting.

Since the CPU does not support big endian in U-mode, this is hardwired to 0.

Since the CPU does not support little endian in U-mode, this is hardwired to 1.
Type

RO	Read-Only Field has a hardwired value that does not change. Writes to an RO field are ignored.

Reset value: 0

`SPIE`

Location

mstatus[5]

Description

Written by hardware in two cases:

Written with prior value of mstatus.SIE when entering (H)S-mode from an exception/interrupt.
Written with the value 1 when returning from an exception via the sret instruction in (H)S-mode or (unlikely) M-mode.

Can also be written by software without immediate side effect.

Other than serving as a record of nested traps as described above, mstatus.SPIE does not affect execution.

Type

Reset value: UNDEFINED_LEGAL

`MIE`

Location

mstatus[3]

Description

Written by hardware in two cases:

Written with the value 0 when entering M-mode from an exception/interrupt.
Written with the prior value of mstatus.MPIE when returning from an exception in M-mode (via mret).

Affects execution by:
When 0, all interrupts are disabled when the current privilege level is M.
When 1, interrupts that are not otherwise disabled with a field in mie are enabled.

Type

RW-H	Read-Write with Hardware update Field is writable by software. Any value that fits in the field is acceptable. Hardware also updates the field without an explicit software write.

Reset value: 0

`SIE`

Location

mstatus[1]

Description

Written by hardware in two cases:

Written with the value 0 when entering (H)S-mode from an exception/interrupt.
Written with the prior value of mstatus.SPIE when returning from an exception via sret in (H)S-mode or (unlikely) M-mode.

Affects execution by:
When 0, all (H)S-mode interrupts are disabled when the current privilege level is (H)S (M-mode interrupts are still enabled).
When 1, (H)S-mode interrupts that are not otherwise disabled with a field in sie are enabled.

Type

Reset value: UNDEFINED_LEGAL