addw :: RISC-V Specification for example_rv64_with

Encoding

Synopsis

Add the 32-bit values in xs1 to xs2, and store the sign-extended result in xd. Any overflow is thrown away.

Access

M

HS

U

VS

VU

Always

Decode Variables

Bits<5> xs2 = $encoding[24:20];
Bits<5> xs1 = $encoding[19:15];
Bits<5> xd = $encoding[11:7];

Execution

Pruned, XLEN == 64
Original

XReg operand1 = %%LINK%func;sext;sext%%(X[xs1], 31);
XReg operand2 = %%LINK%func;sext;sext%%(X[xs2], 31);
X[xd] = %%LINK%func;sext;sext%%(operand1 + operand2, 31);

XReg operand1 = %%LINK%func;sext;sext%%(X[xs1], 31);
XReg operand2 = %%LINK%func;sext;sext%%(X[xs2], 31);
X[xd] = %%LINK%func;sext;sext%%(operand1 + operand2, 31);