S Extension

Implemented Version

1.12.0

Versions

Version 1.11.0

State

ratified

Ratification date

2019-06
Version 1.12.0

State

ratified

Ratification date

2021-12
Version 1.13.0

State

ratified

Ratification date

2024-10

Synopsis

This chapter describes the RISC-V supervisor-level architecture, which contains a common core that is used with various supervisor-level address translation and protection schemes.

Supervisor mode is deliberately restricted in terms of interactions with underlying physical hardware, such as physical memory and device interrupts, to support clean virtualization. In this spirit, certain supervisor-level facilities, including requests for timer and interprocessor interrupts, are provided by implementation-specific mechanisms. In some systems, a supervisor execution environment (SEE) provides these facilities in a manner specified by a supervisor binary interface (SBI). Other systems supply these facilities directly, through some other implementation-defined mechanism.

Instructions

The following instructions are added by this extension in the example_rv64_with_overlay configuration:

sfence.vma

Supervisor memory-management fence

sret

Supervisor Mode Return from Trap

Parameters

This extension has the following implementation options:

ASID_WIDTH

Number of implemented ASID bits. Maximum is 16 for XLEN==64, and 9 for XLEN==32

MSTATUS_FS_LEGAL_VALUES

The set of values that mstatus.FS supports.

MSTATUS_TVM_IMPLEMENTED

Whether or not mstatus.TVM is implemented.

When not implemented mstatus.TVM will be read-only-zero.

MSTATUS_VS_LEGAL_VALUES

The set of values that mstatus.VS will accept from a software write.

MUTABLE_MISA_S

Indicates whether or not the S extension can be disabled with the misa.S bit.

REPORT_ENCODING_IN_STVAL_ON_ILLEGAL_INSTRUCTION

When true, stval is written with the encoding of an instruction that causes an IllegalInstruction exception.

When false stval is written with 0 when an IllegalInstruction exception occurs.

REPORT_VA_IN_MTVAL_ON_INSTRUCTION_PAGE_FAULT

When true, mtval is written with the virtual PC of an instructino when fetch causes an InstructionPageFault.

WHen false, mtval is written with 0 when an instruction fetch causes an InstructionPageFault.

REPORT_VA_IN_MTVAL_ON_LOAD_PAGE_FAULT

When true, mtval is written with the virtual address of a load when it causes a LoadPageFault.

WHen false, mtval is written with 0 when a load causes a LoadPageFault.

REPORT_VA_IN_MTVAL_ON_STORE_AMO_PAGE_FAULT

When true, mtval is written with the virtual address of a store when it causes a StoreAmoPageFault.

WHen false, mtval is written with 0 when a store causes a StoreAmoPageFault.

REPORT_VA_IN_STVAL_ON_BREAKPOINT

When true, stval is written with the virtual PC of the EBREAK instruction (same information as mepc).

When false, stval is written with 0 on an EBREAK instruction.

Regardless, stval is always written with a virtual PC when an external breakpoint is generated

REPORT_VA_IN_STVAL_ON_INSTRUCTION_ACCESS_FAULT

When true, stval is written with the virtual PC of an instructino when fetch causes an InstructionAccessFault.

WHen false, stval is written with 0 when an instruction fetch causes an InstructionAccessFault.

REPORT_VA_IN_STVAL_ON_INSTRUCTION_MISALIGNED

When true, stval is written with the virtual PC when an instruction fetch is misaligned.

When false, stval is written with 0 when an instruction fetch is misaligned.

Note that when IALIGN=16 (i.e., when the C or one of the Zc* extensions are implemented), it is impossible to generate a misaligned fetch, and so this parameter has no effect.

REPORT_VA_IN_STVAL_ON_INSTRUCTION_PAGE_FAULT

When true, stval is written with the virtual PC of an instructino when fetch causes an InstructionPageFault.

WHen false, stval is written with 0 when an instruction fetch causes an InstructionPageFault.

REPORT_VA_IN_STVAL_ON_LOAD_ACCESS_FAULT

When true, stval is written with the virtual address of a load when it causes a LoadAccessFault.

WHen false, stval is written with 0 when a load causes a LoadAccessFault.

REPORT_VA_IN_STVAL_ON_LOAD_MISALIGNED

When true, stval is written with the virtual address of a load instruction when the address is misaligned and MISALIGNED_LDST is false.

When false, stval is written with 0 when a load address is misaligned and MISALIGNED_LDST is false.

REPORT_VA_IN_STVAL_ON_LOAD_PAGE_FAULT

When true, stval is written with the virtual address of a load when it causes a LoadPageFault.

WHen false, stval is written with 0 when a load causes a LoadPageFault.

REPORT_VA_IN_STVAL_ON_STORE_AMO_ACCESS_FAULT

When true, stval is written with the virtual address of a store when it causes a StoreAmoAccessFault.

WHen false, stval is written with 0 when a store causes a StoreAmoAccessFault.

REPORT_VA_IN_STVAL_ON_STORE_AMO_MISALIGNED

When true, stval is written with the virtual address of a store instruction when the address is misaligned and MISALIGNED_LDST is false.

When false, stval is written with 0 when a store address is misaligned and MISALIGNED_LDST is false.

REPORT_VA_IN_STVAL_ON_STORE_AMO_PAGE_FAULT

When true, stval is written with the virtual address of a store when it causes a StoreAmoPageFault.

WHen false, stval is written with 0 when a store causes a StoreAmoPageFault.

SATP_MODE_BARE

Whether or not satp.MODE == Bare is supported.

STVAL_WIDTH

The number of implemented bits in stval.

Must be greater than or equal to max(PHYS_ADDR_WIDTH, VA_SIZE)

STVEC_MODE_DIRECT

Whether or not stvec.MODE supports Direct (0).

STVEC_MODE_VECTORED

Whether or not stvec.MODE supports Vectored (1).

SXLEN

Set of XLENs supported in S-mode. Can be one of:

  • 32: SXLEN is always 32

  • 64: SXLEN is always 64

  • [32, 64]: SXLEN can be changed (via mstatus.SXL) between 32 and 64

S_MODE_ENDIANNESS

Endianness of data in S-mode. Can be one of:

  • little: S-mode data is always little endian

  • big: S-mode data is always big endian

  • dynamic: S-mode data can be either little or big endian, depending on the CSR field mstatus.SBE

TRAP_ON_ECALL_FROM_S

Whether or not an ECALL-from-S-mode causes a synchronous exception.

The spec states that implementations may handle ECALLs transparently without raising a trap, in which case the EEI must provide a builtin.