c.or :: RISC-V Specification for example_rv64_with

Encoding

Synopsis

Or rd with rs2, and store the result in rd The rd and rs2 register indexes should be used as rd+8 and rs2+8 (registers x8-x15). C.OR expands into or rd, rd, rs2.

Access

M

HS

U

VS

VU

Always

Decode Variables

Bits<3> rs2 = $encoding[4:2];
Bits<3> rd = $encoding[9:7];

Execution

Pruned, XLEN == 64
Original

XReg t0 = X[%%LINK%func;creg2reg;creg2reg%%(rd)];
XReg t1 = X[%%LINK%func;creg2reg;creg2reg%%(rs2)];
X[%%LINK%func;creg2reg;creg2reg%%(rd)] = t0 | t1;

XReg t0 = X[%%LINK%func;creg2reg;creg2reg%%(rd)];
XReg t1 = X[%%LINK%func;creg2reg;creg2reg%%(rs2)];
X[%%LINK%func;creg2reg;creg2reg%%(rd)] = t0 | t1;