Implemented Extensions

The following are implemented by the example_rv64_with_overlay configuration:

  • A Atomic instructions

  • Zaamo Load-acquire/Store-release atomic instructions

  • Zalrsc Load-Reserved/Store-Conditional Instructions

  • B Bit Manipulation

  • Zba Address generation

  • Zbb Basic bit-manipulation

  • Zbs Single-bit instructions

  • C Compressed instructions

  • Zca C instructions excluding floating-point loads/stores

  • Zcd Compressed double-precision floating-point loads/stores

  • D Double-precision floating-point

  • F Single-precision floating-point

  • I Base integer ISA (RV32I or RV64I)

  • H Hypervisor

  • M Integer multiply and divide

  • S Supervisor mode

  • Sm Machine mode

  • Smhpm M-mode programmable hardware performance counters

  • Smpmp Physical Memory Protection

  • U User-mode privilege level

  • V Vector Operations

  • Zicntr Base Counters and Timers

  • Zicsr Control and status register instructions

  • Zihpm Hardware Performance Counters

  • Smaia Advanced Interrupt Architecture, M-mode extension

  • Smcdeleg Performance counter delegation

  • Smcntrpmf Cycle and Instret Privilege Mode Filtering

  • Smstateen Machine-mode view of the state-enable extension

  • Ssstateen Supervisor-mode view of the state-enable extension

  • Sscofpmf Counter Overflow and Privilege Mode Filtering

  • Ssaia Advanced Interrupt Architecture, S-mode extension

  • Ssccfg Supervisor-mode counter configuration

  • Sstc Supervisor-mode timer interrupts

  • Sv39 39-bit virtual address translation (3 level)

  • Sv48 48-bit virtual address translation (4 level)

  • Zicboz Cache-block zero instruction

  • Zicbom Cache-block management instructions