hstateen0

Hypervisor State Enable 0 Register

Each bit of a stateen CSR controls less-privileged access to an extension’s state, for an extension that was not deemed "worthy" of a full XS field in sstatus like the FS and VS fields for the F and V extensions.

The number of registers provided at each level is four because it is believed that 4 * 64 = 256 bits for machine and hypervisor levels, and 4 * 32 = 128 bits for supervisor level, will be adequate for many years to come, perhaps for as long as the RISC-V ISA is in use. The exact number four is an attempted compromise between providing too few bits on the one hand and going overboard with CSRs that will never be used on the other.

The stateen registers at each level control access to state at all less-privileged levels, but not at its own level.

When a stateen CSR prevents access to state for a privilege mode, attempting to execute in that privilege mode an instruction that implicitly updates the state without reading it may or may not raise an illegal instruction or virtual instruction exception. Such cases must be disambiguated by being explicitly specified one way or the other. In some cases, the bits of the stateen CSRs will have a dual purpose as enables for the ISA extensions that introduce the controlled state.

With the hypervisor extension, the hstateen CSRs have identical encodings to the mstateen CSRs, except controlling accesses for a virtual machine (from VS and VU modes).

For every bit in an hstateen CSR that is zero (whether read-only zero or set to zero), the same bit appears as read-only zero in sstateen when accessed in VS-mode.

A bit in an hstateen CSR cannot be read-only one unless the same bit is read-only one in the matching mstateen CSR.

Attributes

CSR Address	0x60c
Defining extension	(H && Smstateen && Ssstateen)
Length	64-bit
Privilege Mode	S

CSR Address

0x60c

Defining extension

(H && Smstateen && Ssstateen)

Length

64-bit

Privilege Mode

Format

Figure 1. hstateen0 format

Field Summary

Name Location Type Reset Value

Name	Location	Type	Reset Value
`SE0`	63	RW	UNDEFINED_LEGAL
`ENVCFG`	62	RW	UNDEFINED_LEGAL
`AIA`	59	RW	UNDEFINED_LEGAL
`IMSIC`	58	RW	UNDEFINED_LEGAL
`CTR`	54	RW	0
`FCSR`	1	RW	UNDEFINED_LEGAL
`C`	0	RW	UNDEFINED_LEGAL

SE0

UNDEFINED_LEGAL

ENVCFG

UNDEFINED_LEGAL

AIA

UNDEFINED_LEGAL

IMSIC

UNDEFINED_LEGAL

CTR

FCSR

UNDEFINED_LEGAL

C

UNDEFINED_LEGAL

Fields

`SE0`

Location: hstateen0[63]
Description: The SE0 bit in hstateen0 controls access to the sstateen0 CSR.
Type

RW	Read-Write Field is writable by software. Any value that fits in the field is acceptable and shall be retained for subsequent reads.

Reset value

UNDEFINED_LEGAL

Software write

This field has special behavior when written by software (e.g., through csrrw).

When software tries to write csr_value, the field will be written with the return value of the function below.

if (CSR[mstateen0].SE0 == 1'b0) {
  return 0;
}
return csr_value.SE0;

`ENVCFG`

Location: hstateen0[62]
Description: The ENVCFG bit in hstateen0 controls access to the senvcfg CSRs.
Type

RW	Read-Write Field is writable by software. Any value that fits in the field is acceptable and shall be retained for subsequent reads.

Reset value

UNDEFINED_LEGAL

Software write

This field has special behavior when written by software (e.g., through csrrw).

When software tries to write csr_value, the field will be written with the return value of the function below.

if (CSR[mstateen0].ENVCFG == 1'b0) {
  return 0;
}
return csr_value.ENVCFG;

`AIA`

Location: hstateen0[59]
Description: The AIA bit in hstateen0 controls access to all state introduced by the Ssaia extension and is not controlled by either the CSRIND or the IMSIC bits of hstateen0.
Type

RW	Read-Write Field is writable by software. Any value that fits in the field is acceptable and shall be retained for subsequent reads.

Reset value

UNDEFINED_LEGAL

Software write

This field has special behavior when written by software (e.g., through csrrw).

When software tries to write csr_value, the field will be written with the return value of the function below.

if (CSR[mstateen0].AIA == 1'b0) {
  return 0;
}
return csr_value.AIA;

`IMSIC`

Location: hstateen0[58]
Description: The IMSIC bit in hstateen0 controls access to the guest IMSIC state, including CSRs stopei (really vstopei), provided by the Ssaia extension.

Setting the IMSIC bit in hstateen0 to zero prevents a virtual machine from accessing the hart’s IMSIC the same as setting hstatusVGEIN = 0.
Type

RW	Read-Write Field is writable by software. Any value that fits in the field is acceptable and shall be retained for subsequent reads.

Reset value

UNDEFINED_LEGAL

Software write

This field has special behavior when written by software (e.g., through csrrw).

When software tries to write csr_value, the field will be written with the return value of the function below.

if (CSR[mstateen0].IMSIC == 1'b0) {
  return 0;
}
return csr_value.IMSIC;

`CTR`

Location: hstateen0[54]
Description: If the H extension is implemented and mstateen0.CTR=1, the hstateen0.CTR bit controls access to supervisor CTR state when V=1. This state includes sctrctl (really vsctrctl), sctrstatus, and sireg* (really vsireg*) when siselect (really vsiselect) is in 0x200..0x2FF. hstateen0.CTR is read-only 0 when mstateen0.CTR=0.
Type

RW	Read-Write Field is writable by software. Any value that fits in the field is acceptable and shall be retained for subsequent reads.

Reset value

Software write

This field has special behavior when written by software (e.g., through csrrw).

When software tries to write csr_value, the field will be written with the return value of the function below.

if (CSR[mstateen0].CTR == 1'b0) {
  return 0;
}
return csr_value.CTR;

`FCSR`

Location: hstateen0[1]
Description: The FCSR bit controls access to fcsr for the case when floating-point instructions operate on x registers instead of f registers as specified by the Zfinx and related extensions (Zdinx, etc.). Whenever misa.F = 1, FCSR bit of mstateen0 is read-only zero (and hence read-only zero in hstateen0 and sstateen0 too). For convenience, when the stateen CSRs are implemented and misa.F = 0, then if the FCSR bit of a controlling stateen0 CSR is zero, all floating-point instructions cause an illegal instruction trap (or virtual instruction trap, if relevant), as though they all access fcsr, regardless of whether they really do.
Type

RW	Read-Write Field is writable by software. Any value that fits in the field is acceptable and shall be retained for subsequent reads.

Reset value

UNDEFINED_LEGAL

Software write

This field has special behavior when written by software (e.g., through csrrw).

When software tries to write csr_value, the field will be written with the return value of the function below.

if (CSR[mstateen0].FCSR == 1'b0) {
  return 0;
}
return csr_value.FCSR;

C

Location: hstateen0[0]
Description: The C bit controls access to any and all custom state. The C bit of these registers is not custom state itself; it is a standard field of a standard CSR, either mstateen0, hstateen0, or sstateen0.
Type

RW	Read-Write Field is writable by software. Any value that fits in the field is acceptable and shall be retained for subsequent reads.

Reset value

UNDEFINED_LEGAL

Software write

This field has special behavior when written by software (e.g., through csrrw).

When software tries to write csr_value, the field will be written with the return value of the function below.

if (CSR[mstateen0].C == 1'b0) {
  return 0;
}
return csr_value.C;

Software read

This CSR may return a value that is different from what is stored in hardware.

Pruned
Original

Bits<64> mstateen0_mask = $bits(CSR[CSR[mstateen0]]);
Bits<64> hstateen0_value = $bits(CSR[CSR[hstateen0]]) & mstateen0_mask;
return hstateen0_value;

Bits<64> mstateen0_mask = $bits(CSR[CSR[mstateen0]]);
Bits<64> hstateen0_value = $bits(CSR[CSR[hstateen0]]) & mstateen0_mask;
return hstateen0_value;